ML2721 Ver la hoja de datos (PDF) - Micro Linear Corporation
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ML2721 Datasheet PDF : 27 Pages
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PRELIMINARY
CONTROL INTERFACES AND REGISTER DESCRIPTION (continued)
ML2721
Data Bit
B15 (MSB) / DB13
B14 / DB12
B13 / DB11
B12 / DB10
B11 / DB9
B10 / DB8
B9 / DB7
B8 / DB6
B7 / DB5
B6 / DB4
B5 / DB3
B4 / DB2
B3 / DB1
B2 / DB0
B1 / ADB1
B0 (LSB) / ADB0
Name
TMODE
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DTM2
DTM1
DTM0
ATM2
ATM1
ATM0
ADR1
ADR0
Description
Tune filter Select Bit
Use
Set TMODE to 0 for Normal Operation
Set All Bits to 0 (zero)
Digital Test Control Bits
See Table 13
Analog Test Control Bits
MSB Addrees Bit
LSB Addrees Bit
ADR1 = 1
ADR0 = 0
See Table 12
Table 9C. Register 2 — Filter Tuning Select and Test Mode Register
Serial Interface
Data and clock signals are ignored when EN is high.
When EN is low data on the DATA pin is clocked into a
shift register by rising edges on the CLK pin. The
information is latched when EN goes high. This serial
interface bus is similar to that commonly found on PLL
devices. It can be efficiently programmed by either byte
or 16-bit word oriented serial bus hardware. The data
latches are implemented in static CMOS and use minimal
power when the bus is inactive. Figure 9 and Table 10
provide timing and register programming illustrations.
tF
tS
tH
tR
Symbol
tR
tF
tCK
tW
tD
Parameter
Clock input rise time
Minimum pulse width
Time (ns)
15
15
>50
2000
>15
tSE
>15
tS
>15
tH
Data-to-clock hold time
>15
Table 10. 3-Wire Bus Timing Characteristics
tSE
tCK
tD
CLK
DATA
EN
MSB
DB13
DB12
DB11
REGISTER DATA (14 BITS)
LSB
DB0
ADR1
ADR0
tW
ADDRESS DATA (2 BITS)
Figure 9. Serial Bus Timing for Address and Data Programming
January, 2000 PRELIMINARY DATASHEET
19
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