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ML9058E

132-Channel LCD Driver with Built-in RAM for LCD Dot Matrix Displays

LAPIS Semiconductor Co., Ltd. 

LAPIS Semiconductor

FEDL9058E-01

ML9058E

Parameter

Address hold time

Address setup time

System cycle time

Data setup time

Data hold time

Access time

Output disable time

Enable H pulse width

Enable L pulse width

Read

Write

Read

Write

Symbol

tAH6

tAW6

tCYC6

tDS6

tDH6

tACC6

tOH6

tEWHR

tEWHW

tEWLR

tEWLW

[VDD = 4.5 to 5.5 V, Tj = –40 to +85°C]

Condition

Rated value

Unit

Min Max

5

—

5

—

166 —

30 —

10 —

CL = 100 pF

— 70 ns

10 50

70 —

30 —

60 —

60 —

Parameter

Address hold time

Address setup time

System cycle time

Data setup time

Data hold time

Access time

Output disable time

Enable H pulse width

Enable L pulse width

Read

Write

Read

Write

Symbol

tAH6

tAW6

tCYC6

tDS6

tDH6

tACC6

tOH6

tEWHR

tEWHW

tEWLR

tEWLW

[VDD = 3.7 to 4.5 V, Tj = –40 to +85°C]

Condition

Rated value

Unit

Min Max

5

—

5

—

300 —

40 —

15 —

CL = 100 pF

— 140 ns

10 100

120 —

60 —

60 —

60 —

Note 1:

Note 2:

Note 3:

The input signal rise and fall times are specified as 15ns or less.

When using the system cycle time for fast speed, the specified values are (tr + tf)  (tCYC6 –

tEWLW – tEWHW) or (tr + tf)  (tCYC6 – tEWLR – tEWHR).

All timings are specified taking the levels of 20% and 80% of VDD as the reference.

The values of tEWLW and tEWLR are specified during the overlapping period of CS1 at “L” (CS2 =

“H”) and the “H” level of E.

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