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ML9058E

132-Channel LCD Driver with Built-in RAM for LCD Dot Matrix Displays

LAPIS Semiconductor Co., Ltd. 

LAPIS Semiconductor

FEDL9058E-01

ML9058E

Number

Function Pin name of pins I/O

CL

1

I/O

Display

timing

generator

circuit

FR

1

I/O

DOF

1

I/O

FRS

1

O

IRS

Power

supply

circuit

VDD

VSS

VIN

1

I

12

—

12

—

—

5

Description

This is the clock input/output pin.

The function of this pin will be as follows depending on the states of

M/S and CLS signals.

M/S

CLS

CL

“H”

Output

“H”

“L”

Input

“H”

Input

“L”

“L”

Input

When the ML9058E is used in the master/slave mode, the

corresponding CL pin has to be connected.

This is the input/output pin for LCD display frame reversal signal.

M/S = “H”: Output

M/S = “L”: Input

When the ML9058E is used in the master/slave mode, the

corresponding FR pin has to be connected.

This is the blanking control pin for the LCD display.

M/S = “H”: Output

M/S = “L”: Input

When the ML9058E is used in the master/slave mode, the

corresponding DOF pin has to be connected.

This is the output pin for static drive.

This pin is used in combination with the FR pin.

This is the pin for selecting the resistor for adjusting the voltage V1.

IRS = “H”: The internal resistor is used.

IRS = “L”: The internal resistor is not used. The voltage V1 is

adjusted using the external potential divider resistors connected to

the pins VR. This pin is effective only in the master operation. This

pin is tied to the “H” or the “L” level during slave operation.

These pins are tied to the MPU power supply pin VCC.

These are the 0 V pins connected to the system ground (GND).

These are the reference power supply pins of the voltage multiplier

circuit for driving the LCD.

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