ML9058E Ver la hoja de datos (PDF) - LAPIS Semiconductor Co., Ltd.
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ML9058E
LAPIS Semiconductor Co., Ltd.
ML9058E Datasheet PDF : 76 Pages
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LAPIS Semiconductor
FEDL9058E-01
ML9058E
FUNCTIONAL DESCRIPTION
MPU Interface
MPU
80-Series
68-Series
Read mode
Pin RD = “L”
Pin R/W = “H”
Pin E = “H”
Write mode
Pin WR = “L”
Pin R/W = “L”
Pin E = “H”
In the case of the 80-series MPU interface, a command is started by applying a low pulse to the RD pin or the WR
pin.
In the case of the 68-series MPU interface, a command is started by applying a high pulse to the E pin.
Selection of interface type
The ML9058E carries out data transfer using either the 8-bit bi-directional data bus (DB0 to DB7) or the serial data
input line (SI). Either the 8-bit parallel data input or serial data input can be selected as shown in Table 2 by setting
the P/S pin to the “H” or the “L” level.
Table 2 Selection of interface type (parallel/serial)
P/S
CS1
CS2
A0
H: Parallel input CS1
CS2
A0
L: Serial input
CS1
CS2
A0
RD
WR
C86
D7
D6 DB0 to DB5
RD
WR
C86
D7
D6 DB0 to DB5
—
—
—
SI
SCL
—
A hyphen (—) indicates that the pin can be tied to the “H” or the “L” level.
Parallel interface
When the parallel interface is selected, (P/S = “H”), it is possible to connect this LSI directly to the MPU bus of
either an 80-series MPU or a 68-series MPU as shown in Table 3. depending on whether the pin C86 is set to “H”
or “L”.
Table 3 Selection of MPU during parallel interface (80–/68–series)
C86
H: 68-Series MPU bus
L: 80-Series MPU bus
CS1
CS2
A0
CS1
CS2
A0
CS1
CS2
A0
RD
WR
DB0 to DB7
E
R/W
DB0 to DB7
RD
WR
DB0 to DB7
The data bus signals are identified as shown in Table 4 below depending on the combination of the signals A0, RD
(E), and WR (R/W) of Table 3.
Table 4 Identification of data bus signals during parallel interface
Display data read
Display data write
Status read
Control data write (command)
Common
A0
1
1
0
0
68-Series
R/W
1
0
1
0
80-Series
RD
WR
0
1
1
0
0
1
1
0
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