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ML9058E

132-Channel LCD Driver with Built-in RAM for LCD Dot Matrix Displays

LAPIS Semiconductor Co., Ltd. 

LAPIS Semiconductor

FEDL9058E-01

ML9058E

Serial Interface Timing Characteristics

 Serial interface

CS1

(CS2 = “1”)

A0

SCL

SI

tCSS

VIL

tCSH

VIL

tSAS

VIH

VIL

tSAH

VIH

VIL

tSCYC

VIH

tSLW

VIH

VIH

VIL

VIL

tSHW

VIL

tf

tr

tSDS

VIH

VIL

tSDH

VIH

VIL

Parameter

Serial clock period

SCL “H” Pulse width

SCL “L” Pulse width

Address setup time

Address hold time

Data setup time

Data hold time

CS setup time

CS hold time

Symbol

tSCYC

tSHW

tSLW

tSAS

tSAH

tSDS

tSDH

tCSS

tCSH

[VDD = 4.5 to 5.5 V, Tj = –40 to +85°C]

Condition

Rated value

Unit

Min Max

200 —

75 —

75 —

50 —

100 — ns

50 —

50 —

100 —

100 —

Note 1: The input signal rise and fall times are specified as 15ns or less.

Note 2: All timings are specified taking the levels of 20% and 80% of VDD as the reference.

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