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P4C1981-10JC

ULTRA HIGH SPEED 16K x 4 CMOS STATIC RAMS

Performance Semiconductor 

P4C1981/1981L, P4C1982/1982L

P4C1981/P4C1981L, P4C1982/P4C1982L

ULTRA HIGH SPEED 16K x 4

CMOS STATIC RAMS

FEATURES

Full CMOS, 6T Cell

High Speed (Equal Access and Cycle Times)

– 10/12/15/20/25 ns (Commercial)

– 12/15/20/25/35 ns (Industrial)

– 15/20/25/35/45 ns (Military)

Low Power Operation (Commercial/Military)

– 715 mW Active – 12/15

– 550/660 mW Active – 20/25/35/45

– 193/220 mW Standby (TTL Input)

– 83/110 mW Standby (CMOS Input) P4C1981/1981L

– 5.5 mW Standby (CMOS Input)

P4C1981L/82L (Military)

Output Enable and Dual Chip Enable Functions

5V ± 10% Power Supply

Data Retention with 2.0V Supply, 10 µA Typical

Current (P4C1981L/1982L (Military)

Separate Inputs and Outputs

– P4C1981/L Input Data at Outputs during Write

– P4C1982/L Outputs in High Z during Write

Fully TTL Compatible Inputs and Outputs

Standard Pinout (JEDEC Approved)

– 28-Pin 300 mil DIP, SOJ

– 28-Pin 350 x 550 mil LCC

DESCRIPTION

The P4C1981/L and P4C1982/L are 65,536-bit (16Kx4)

ultra high-speed static RAMs similar to the P4C198, but

with separate data I/O pins. The P4C1981/L feature a

transparent write operation when OE is low; the outputs of

the P4C1982/L are in high impedance during the write

cycle. All devices have low power standby modes. The

RAMs operate from a single 5V ± 10% tolerance power

supply. With battery backup, data integrity is maintained

for supply voltages down to 2.0V. Current drain is typically

10 µA from 2.0V supply.

Access times as fast as 10 nanoseconds are available,

permitting greatly enhanced system operating speeds.

CMOS is used to reduce power consumption to a low 715

mW active, 193 mW standby. For the P4C1982L and

P4C1981L, power is only 5.5 mW standby with CMOS

input levels. The P4C1981/L and P4C1982/L are mem-

bers of a family of PACE RAM™ products offering fast

access times.

The P4C1981/L and P4C1982/L are available in 28-pin

300 mil DIP and SOJ, and in 28-pin 350x550 mil LCC

packages providing excellent board level densities.

FUNCTIONAL BLOCK DIAGRAM

A

(8)

A

ROW

SELECT

65,536-BIT

MEMORY

ARRAY

I1

O1

I2

INPUT

O2

I3

DATA

CONTROL

COLUMN I/O

O3

I4

O4

COLUMN

SELECT

CE1

CE2

A

A

(6)

WE

P4C1982

OE

P4C1981

PIN CONFIGURATIONS

A0 1

A1 2

A2 3

A3 4

A4 5

A5 6

A6 7

A7 8

A8 9

I1 10

I2 11

CE1 12

OE 13

GND 14

28 VCC

27 A13

26 A12

25 A11

24 A10

23 A9

22 I4

21 I3

20 O4

19 O3

18 O2

17 O1

16 WE

15 CE2

3

27

A3

4

2

28 26 A12

A4 5

1

25 A11

A5 6

24 A10

A6 7

23 A9

A7 8

22 I4

A8 9

21 I3

I1 10

20 O4

I2 11

19 O3

CE1 12 14 15 16 18 O2

13

17

DIP (P5, D5-2), SOJ (J5)

TOP VIEW

P4C1981/ 1982

LCC (L5)

TOP VIEW

Means Quality, Service and Speed

1Q97

81

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