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P4C1981-10JC

ULTRA HIGH SPEED 16K x 4 CMOS STATIC RAMS

Performance Semiconductor 

P4C1981/1981L, P4C1982/1982L

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

Input Rise and Fall Times

Input Timing Reference Level

3ns

1.5V

Output Timing Reference Level

1.5V

Output Load

See Figures 1 and 2

TRUTH TABLE

P4C1981/L (P4C1982/L)

CE

1

CE

2

WE

OE

Mode

H X X X Standby

Output

High Z

X H X X Standby

High Z

L L H H Output Inhibit High Z

L L H L READ

L L L H WRITE

D

OUT

High Z

L L L L WRITE

DIN (High Z)

DOUT

255Ω

+5V

480Ω

3300ppFF* *(5(p5Fp* fFoHr*tZH,foZtL,rZt,LtZ, tOHZ, tOLZ,

tWtWZaZnanddOttOW)W)

DOUT

RTH = 166.5Ω

VTH = 1.73V

30pF* (5pF* for tHZ, tLZ, tOHZ, tOLZ,

tWZ and tOW)

Figure 1. Output Load

* including scope and test fixture.

Note:

Because of the ultra-high speed of the P4C1981/L and P4C1982/L, care

must be taken when testing this device; an inadequate setup can cause

a normal functioning part to be rejected as faulty. Long high-inductance

leads that cause supply bounce must be avoided by bringing the VCC and

ground planes directly up to the contactor fingers. A 0.01 µF high

Figure 2. Thevenin Equivalent

frequency capacitor is also required between VCC and ground. To avoid

signal reflections, proper termination must be used; for example, a 50Ω

test environment should be terminated into a 50Ω load with 1.73V

(Thevenin Voltage) at the comparator input, and a 116Ω resistor must be

used in series with DOUT to match 166Ω (Thevenin Resistance).

88

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