Features
• Generates the Host and Memory clocks required for 2-way and 4-way multi-processor (MP) clockpartitioned platforms, including:
   ◆ Six differential current-mode Host clock pairs
   ◆ Two 3.3V Memory Reference clocks
   ◆ 66.67MHz and 14.318MHz 3.3V Reference clocks for the FS6159 device
   ◆ Three optional 33.3MHz 1.8V APIC clocks
• Control of current-mode Host clocks via IREF current programming pin and ISEL_0:1 current multiplier pins
• Optional APIC clocks enabled via APICON input (see Table 5 for Pins 21-23 configuration)
• Host clock frequency selection via the SEL_A, SEL_B, and SEL133/100# pins
• Active-low PWR_DWN# signal allows one complete clock cycle on each clock outputs and then shuts down the crystal oscillator, PLL, and disables outputs
• Spread-spectrum modulation (-0.5% at 31.5kHz) of Host, Memory, APIC, and 66MHz Reference clocks, enabled via SS_EN# input
• Supports test mode and tristate output control to facilitate board testing
• Available in a 48-pin SSOP and TSSOP