[ESMT]

GENERAL DESCRIPTION
  The M32L1632512A is 16, 777, 216 bits synchronous high data rate Dynamic RAM organized as 2 x 262, 144 words by 32 bits, fabricated with ESMT’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies , programmable burst length, and programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.

FEATURES
  JEDEC standard 3.3V power supply
  LVTTL compatible with multiplexed address
  Dual bank / Pulse RAS
  MRS cycle with address key programs
    - CAS Latency ( 2, 3 )
    - Burst Length ( 1, 2, 4, 8 & full page )
    - Burst Type ( Sequential & Interleave )
  All inputs are sampled at the positive going edge of the system clock
  Burst Read Single-bit Write operation
  DQM 0-3 for byte masking
  Auto & self refresh
  32ms refresh period (2K cycle)
  100 pin QFP