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MX98728EC

GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION

Macronix International 

MX98728EC

Missed Packet Counter: MPCL (Reg07/06h), R/W, default=0000h

Bit

6.7-0

7.7-0

Symbol

MISSCNT[7:0]*

MISSCNT[15:8]*

Description

Miss Packet Counter Bits [7:0]: Lower byte of the Miss packet counter.

Miss Packet Counter Bits [15:8]: Upper byte of the Miss packet counter.

Interrupt Mask Register: IMR (Reg.08h), R/W, default=00h

Bit

Symbol

Description

8.0

FRAGIM Fragment Counter Interrupt Mask: Set to enable the host DMA Fragment counter ( FRAGI)

interrupt. Default is reset which disable the FRAGI interrupt.When AUTORCVR is set,

this bit should be reset.

8.1

RIM

Received Interrupt Mask: Set to enable the Packet Received Interrupt. Default is reset

which disables the RI interrupt.

8.2

TIM

Transmit Interrupt Mask: Set to enable the Packet transmit OK interrupt. Default is reset

which disables the TI interrupt.

8.3

REIM

Receive Error Interrupt Mask: Set to enable the Receive Error interrupt. Default is reset

which disables the REI interrupt.

8.4

TEIM

Transmit Error Interrupt Mask: Set to enable transmit error interrupt. Default is reset

which disables the TEI interrupt.

8.5

FIFOEIM FIFO Error Interrupt Mask: Set to enable the FIFO Error interrupt. Default is reset which

disables the FIFOEI interrupt. When AUTORCVR is set, this bit should be reset.

8.6

BUSEIM Bus Error Interrupt Mask: Set to enable the Bus Error interrupt. Default is reset which

disables the BUSEI interrupt.

8.7

RBFIM

RX Buffer Full Interrupt Mask: Set to enable the RX Buffer full interrupt. Default is reset

which disables the BFI interrupt.

P/N:PM0723

REV. 1.0, JUL. 13, 2000

13

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