MX98728EC Ver la hoja de datos (PDF) - Macronix International
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MX98728EC
Macronix International
MX98728EC Datasheet PDF : 71 Pages
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MX98728EC
GMAC Configuration A Register: GCA (Reg 32h), R/W, default=00h
Bit Symbol
32.0 BPSCRM
32.1 PBW
32.2 SLOWSRAM
32.3 ARXERRB
32.4 MIISEL
32.5 AUTOPUB
32.6 TXFIFOCNTEN
32.7 RESERVED
Description
Bypass Scrambler: Default is 0, meaning enable the 100 TX scrambler. Set to disable the
scrambler for the 100 TX mode.
Packet Buffer Data Width : Default is 0, meaning the packet buffer data width is byte. Set
when the packet buffer data width is 16 bits.
Normally reset, SRAM Taa must be less than 25ns, set to use -70ns SRAM or better
Accept RX packet with error : Default is reset to receive packets with error, set to reject
packets with error, packet memory will not contain packet with RW, FO, CRC errors.
Default = 0 after reset, on-chip tranceiver is used. Set by software to enable MII interface.
Auto Page Update option :
Set to disable the automatic host page update during the host DMAs. Reset to enable the
host page update for the RRP, TWP registers. Default is reset.
Default=0, after rest which means Reg 3E & 3F (TXFIFOCNT) are not used. This option is
only good for a byte-base host transfer. For host which do word/double word transfer, this
bit must be set to 1 to force TXFIFO use actual packet length for transmission.
Default = 0.
GMAC Configuration B Register: GCB (Reg33h), R/W, default=00h
Bit
33.1-0
33.3-2
33.4
33.5
33.6
33.7
Symbol
TTHD[1:0]
RTHD[1:0]
SRAMELEN
X4ELEN
DREQB2EN
reserved
Description
Transmit FIFO Threshold : Default is 00
TTHD1
TTHD0
FIFO depth aggressiveness
0
0
1/2
medium
0
1
1/4
least
1
0
3/4
more
1
1
reserved
reserved
Receive FIFO Threshold : Default is 00
RTHD1
RTHD0
FIFO depth aggressiveness
0
0
1/2
medium
0
1
1/4
most
1
0
3/4
least
1
1
reserved
SRAM Early Latch Enable : Default = 0. Set to enable.
X4 FIFO Early Latch Enable : Defautl = 0. Set to enable.
DREQB NEW Timing Enable : Default = 0. Set to enable.
P/N:PM0723
REV. 1.0, JUL. 13, 2000
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