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MX98728EC

GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION

Macronix International 

MX98728EC

Interrupt Register: IR (Reg09h), R/W, default=00h

Bit

Symbol

Description

9.0

FRAGI* Fragment Counter Interrupt : Set to assert the interrupt when the host DMA Fragment

Counter is less than current received packet length. Writing 1 to this bit will clear the bit

and the interrupt. Writing 0 has no effect.

9.1

RI*

Receive OK Interrupt : Set to assert the interrupt. Writing 1 to this bit will clear the bit and

the interrupt. Writing 0 has no effect. The assertion timing of RI can be programmed

through the Reg50.4 bit (RINTSEL) for either the completion of the host receive DMA

activity or the completion of the receive local DMA activity.

9.2

TI*

Transmit OK Interrupt: Set to assert the interrupt.Writing 1 to this bit will clear the bit and

the interrupt. Writing 0 has no effect.

9.3

REI*

Receive Error Interrupt: Set to assert the interrupt when the packet is received with error

. Writing 1 to this bit will clear the bit and the interrupt. Writing 0 has no effect. The

assertion timing of RI can be programmed through the Reg50.4 bit (RINTSEL) for either

the completion of the host receive DMA activity or the completion of the receive local

DMA activity.

9.4

TEI*

Transmit Error Interrupt : Set to assert the interrupt when the packet is transmitted with

error. Writing 1 to this bit will clear the bit and the interrupt. Writing 0 has no effect.

9.5

FIFOEI* FIFO Error Interrupt: Set to assert the interrupt when either the TX FIFO is overrun or the

RX FIFO is overrun. Writing 1 to this bit will clear the bit and the interrupt. Writing 0 has

no effect.

9.6

BUSEI* Bus Error Interrupt: Set to assert the interrupt when the Bus integrity check is enabled

and failed. Writing 1 to this bit will clear the bit and the interrupt. Writing 0 has no effect.

9.7

RBFI*

RX Buffer Full Interrupt: Set to assert the interrupt when the RX buffer area is being

overwritten by new received packets. Writing 1 to this bit will clear the bit and the inter-

rupt. Writing 0 has no effect.

Note : All page pointer bits [11:0] are mapped to MA[19:8] with the same bit ordering.

P/N:PM0723

REV. 1.0, JUL. 13, 2000

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