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MX98728EC

GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION

Macronix International 

MX98728EC

Network Address Filtering Registers : Reg20h~25h (R/W), 26h~2Dh (R/W), default=00h

Bit

20.[7:0]

21.[7:0]

22.[7:0]

23.[7:0]

24.[7:0]

25.[7:0]

26.[7:0]

27.[7:0]

28.[7:0]

29.[7:0]

2A.[7:0]

2B.[7:0]

2C.[7:0]

2D.[7:0]

Symbol

PAR0

PAR1

PAR2

PAR3

PAR4

PAR5

MAR0

MAR1

MAR2

MAR3

MAR4

MAR5

MAR6

MAR7

Description

Physical Address Register Byte 0: PAR [7:0]

Physical Address Register Byte 1: PAR [15:8]

Physical Address Register Byte 2 : PAR [23:16]

Physical Address Register Byte 3 : PAR [31:24]

Physical Address Register Byte 4 : PAR [39:32]

Physical Address Register Byte 5 : PAR [47:40]

Hash Table Register Byte 0 : MAR [7:0]

Hash Table Register Byte 1 : MAR [15:8]

Hash Table Register Byte 2 : MAR [23:16]

Hash Table Register Byte 3 : MAR [31:24]

Hash Table Register Byte 4 : MAR [39:32]

Hash Table Register Byte 5 : MAR [47:40]

Hash Table Register Byte 6 : MAR [56:48]

Hash Table Register Byte 7 : MAR [63:57]

Transceiver Control Register : ANALOG (Reg 2Eh), R/W, default=07h

Bit

2E.0

2E.1

2E.2

2E.3

2E.4

2E.5

2E.6-7

Symbol

DS120

DS130

PWD10B

PWD100

RSQ

RST100

Reserved

Description

Must be 1 for NORMAL mode with auto-compensation.

Must be 1 for NORMAL mode with auto-compensation

Set for NORMAL mode, write 0 followed by write 1 will power down 10 Base-T

analog circuit.

Reset for NORMAL mode, write 1 followed by write 0 will power down 100 Base-

T analog circuit.

Reduced SQuelch Enable : Set to enable the reduced squelch circuit in the 10

Base-T mode for the receive channel. This can help the reception in a long cable

application. Default is reset, meaning the normal CAT-5 cable is used.

Reset for NORMAL mode, write 1 followed by write 0 will reset 100 Bare-T analog

circuit.

must be zero.

DMA Interval Timer : DINTVAL (Reg 2Fh), R/W, default=00h

Bit

2F.7-0

Symbol

DINTVAL

Description

DMA Interval Timer : Used to control the latency between the two consecutive

DMA read burst cycles. Default is all zero, meaning this function is disabled. A

non-zero value tells GMAC to prepare the next host DMA read close to the timer's

expiration. This timer will improve the Host DMA read access priority. The timer's

time base is 0.5Mhz, which gives a maximum of 512us.

P/N:PM0723

REV. 1.0, JUL. 13, 2000

18

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