LPC47N227-MN Ver la hoja de datos (PDF) - SMSC -> Microchip

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LPC47N227-MN

100 Pin Super I/O with LPC Interface for Notebook Applications

SMSC -> Microchip 

Note 5: The GP11/SYSOPT pin requires an external pulldown resistor to put the base IO address for

configuration at 0x02E. An external pullup resistor is required to move the base IO address

for configuration to 0x04E.

Note 6: VCC must not be greater than 0.5V above VTR.

Note 7: This pin is output only and is powered by VTR.

Note 8: Ring indicator pins nRI1 and nRI2 have input buffers into the wakeup logic that are powered by

VTR. These pins are also inputs to VCC powered logic.

Note 9: GP10-GP17, GP20-GP24 and GP30-GP37 pins have input buffers into the wakeup logic that

are powered by VTR. GP40-47 pins are powered by VCC even as inputs.

Buffer Type Description

I

IS

O6

O8

OD8

IO8

O12

OD12

IO12

OD14

OP14

IOP14

PCI_I

PCI_O

PCI_OD

PCI_IO

PCI_ICLK

Input TTL Compatible.

Input with Schmitt Trigger.

Output, 6mA sink, 3mA source.

Output, 8mA sink, 4mA source.

Open Drain Output, 8mA sink.

Input/Output, 8mA sink, 4mA source.

Output, 12mA sink, 6mA source.

Open Drain Output, 12mA sink.

Input/Output, 12mA sink, 6mA source.

Open Drain Output, 14mA sink.

Output, 14mA sink, 14mA source.

Input/Output, 14mA sink, 14mA source. Backdrive protected.

Input. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1)

Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1)

Open Drain Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1)

Input/Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1)

Clock Input. These pins meet the PCI 3.3V AC and DC Characteristics and timing. (Note

2)

Note 1. See the PCI Local Bus Specification, Revision 2.1, Section 4.2.2.

Note 2. See the PCI Local Bus Specification, Revision 2.1, Section 4.2.2. and 4.2.3.

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