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LPC47N227-MN

100 Pin Super I/O with LPC Interface for Notebook Applications

SMSC -> Microchip 

Power Management

CLOCKRUN Protocol

See the Low Pin Count (LPC) Interface

Specification Reference, Section 8.1.

LPCPD Protocol

The LPC47N227 will function properly if the

nLPCPD signal goes active and then inactive

again without nPCI_RESET becoming active.

This is a requirement for notebook power

management functions.

Although the LPC Bus spec 1.0 section 8.2

states, "After nLPCPD goes back inactive, the

LPC I/F will always be reset using nLRST”, this

statement does not apply for mobile systems.

nLRST (nPCI_RESET) will not occur if the LPC

Bus power was not removed. For example,

when exiting a "light" sleep state (ACPI S1, APM

POS), nLRST (nPCI_RESET) will not occur.

When exiting a "deeper" sleep state (ACPI S3-

S5, APM STR, STD, soft-off), nLRST

(nPCI_RESET) will occur.

The nLPCPD pin is implemented as a “local”

powergood for the LPC interface in the

LPC47N227. It is not used as a global

powergood for the chip. It is used to reset the

LPC block and hold it in reset.

An internal powergood is implemented in

LPC47N227 to minimize power dissipation in the

entire chip.

Prior to going to a low-power state, the system

will assert the nLPCPD signal. It will go active at

least 30 microseconds prior to the LCLK

(PCI_CLK) signal stopping low and power being

shut to the other LPC I/F signals.

Upon recognizing nLPCPD active, the

LPC47N227 will tri-state the nLDRQ signal and

do so until nLPCPD goes back active.

Upon recognizing nLPCPD inactive, the

LPC47N227 will drive its nLDRQ signal high.

See the Low Pin Count (LPC) Interface

Specification Reference, Section 8.2.

SYNC Protocol

See the Low Pin Count (LPC) Interface

Specification Reference, Section 4.2.1.8 for a

table of valid SYNC values.

Typical Usage

The SYNC pattern is used to add wait states.

For read cycles, the LPC47N227 immediately

drives the SYNC pattern upon recognizing the

cycle. The host immediately drives the sync

pattern for write cycles. If the LPC47N227 needs

to assert wait states, it does so by driving 0101

or 0110 on LAD[3:0] until it is ready, at which

point it will drive 0000 or 1001. The LPC47N227

will choose to assert 0101 or 0110, but not switch

between the two patterns.

The data (or wait state SYNC) will immediately

follow the 0000 or 1001 value.

The SYNC value of 0101 is intended to be used

for normal wait states, wherein the cycle will

complete within a few clocks. The LPC47N227

uses a SYNC of 0101 for all wait states in a DMA

transfer.

The SYNC value of 0110 is intended to be used

where the number of wait states is large. This is

provided for EPP cycles, where the number of

wait states could be quite large (>1

microsecond). However, the LPC47N227 uses a

SYNC of 0110 for all wait states in an I/O

transfer.

The SYNC value is driven within 3 clocks.

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