LPC47N227-MN Ver la hoja de datos (PDF) - SMSC -> Microchip

Número de pieza

componentes Descripción

Lista de partido

LPC47N227-MN

100 Pin Super I/O with LPC Interface for Notebook Applications

SMSC -> Microchip 

LPC Interface

LPC Interface Signal Definition

The following sub-sections specify the

implementation of the LPC bus.

The signals required for the LPC bus interface

are described in the table below. LPC bus

signals use PCI 33MHz electrical signal

characteristics.

SIGNAL NAME

LAD[3:0]

nLFRAME

nPCI_RESET

nLDRQ

nIO_PME

nLPCPD

SER_IRQ

PCI_CLK

nCLKRUN

TYPE

I/O

Input

Input

Output

OD

Input

I/O

Input

I/OD

DESCRIPTION

LPC address/data bus. Multiplexed command, address and

data bus.

Frame signal. Indicates start of new cycle and termination of

broken cycle

PCI Reset. Used as LPC Interface Reset.

Encoded DMA/Bus Master request for the LPC interface.

Power Mgt Event signal. Allows the LPC47N227 to request

wakeup.

Powerdown Signal. Indicates that the LPC47N227 should

prepare for power to be shut on the LPC interface.

Serial IRQ.

PCI Clock.

Clock Run. Allows the LPC47N227 to request the stopped

PCI_CLK be started.

LPC Cycles

The following cycle types are supported by the

LPC protocol.

CYCLE TYPE

I/O Write

I/O Read

DMA Write

DMA Read

TRANSFER SIZE

1 Byte

1 Byte

1 Byte

1 Byte

Count (LPC) Interface Specification Revision 1.0

from Intel, Section 4.2 for definition of these

fields.

nLFRAME Usage

nLFRAME is used by the host to indicate the

start of cycles and the termination of cycles due

to an abort or time-out condition. This signal is

to be used by the LPC47N227 to know when to

monitor the bus for a cycle.

The LPC47N227 ignores cycles that it does not

support.

This signal is used as a general notification that

the LAD[3:0] lines contain information relative to

Field Definitions

the start or stop of a cycle, and that the

LPC47N227 monitors the bus to determine

The data transfers are based on specific fields

that are used in various combinations, depending

on the cycle type. These fields are driven onto

the LAD[3:0] signal lines to communicate

address, control and data information over the

LPC bus between the host and the LPC47N227.

whether the cycle is intended for it. The use of

nLFRAME allows the LPC47N227 to enter a

lower power state internally. There is no need

for the LPC47N227 to monitor the bus when it is

inactive, so it can decouple its state machines

from the bus, and internally gate its clocks.

See

the

Low

Pin

When the LPC47N227 samples nLFRAME

active, it immediately stops driving the LAD[3:0]

signal lines on the next clock and monitor the bus

for new cycle information.

17

Share Link: