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SC18IM700

Master I2C-bus controller with UART interface

NXP Semiconductors. 

NXP Semiconductors

SC18IM700

Master I2C-bus controller with UART interface

host sends

S CHAR.

SLAVE ADR.

+W

NUMBER

OF BYTES

DATA 0

Fig 3. Write N bytes to slave device

DATA N P CHAR.

002aac048

7.1.2 Read N byte from slave device

The host issues the read command by sending an S character followed by an I2C-bus

slave device address, and the total number of bytes to be read from the addressed

I2C-bus slave. The frame is then terminated with a P character. Once the host issues this

command, the SC18IM700 will access the I2C-bus slave device, get the correct number of

bytes from the addressed I2C-bus slave, and then return the data to the host.

Note that the second byte sent is the I2C-bus device slave address. The least significant

bit (R) of this byte must be set to 1 to indicate this is an I2C-bus write command.

host sends

S CHAR.

SLAVE ADR.

+R

NUMBER

OF BYTES

P CHAR.

18IM responds

DATA 0

DATA N

Fig 4. Read N byte from slave device

002aac049

7.1.3 Write to 18IM internal register

The host issues the internal register write command by sending a W character followed by

the register and data pair. Each register to be written must be followed by the data byte.

The frame is then terminated with a P character.

W CHAR. REGISTER 0

DATA 0

Fig 5. Write to 18IM internal register

REGISTER N

DATA N

P CHAR.

002aac050

Remark: Write and read from the internal 18IM register is processed immediately as soon

as the intended register is determined by 18IM.

SC18IM700_3

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3 — 12 October 2017

© NXP Semiconductors N.V. 2017. All rights reserved.

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