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AD8151

33 × 17, 3.2 Gbps Digital Crosspoint Switch

Analog Devices 

AD8151

CONTROL INTERFACE TIMING DIAGRAMS

CS INPUTS

WE INPUTS

A[4:0] INPUTS

D[6:0] INPUTS

tCSW

tASW

tCHW

tWP

tAHW

tDSW

tDHW

Figure 27. First Rank Write Cycle

Table 6. First Rank Write Cycle

Parameter

Mnemonic

Setup Time

tCSW

tASW

tDSW

Hold Time

tCHW

tAHW

tDHW

Enable Pulse

tWP

Description

Chip select to write enable

Address to write enable

Data to write enable

Chip select from write enable

Address from write enable

Data from write enable

Width of write enable pulse

Conditions

TA = 25°C

VDD = 5 V

VCC = 3.3 V

Min Typ Max Unit

0

ns

0

ns

15

ns

0

ns

0

ns

0

ns

15

ns

CS INPUTS

UPDATE INPUTS

ENABLING

OUT[0:16][N:P]

OUTPUTS

DATA FROM RANK 1

TOGGLE

OUT[0:16][N:P]

OUTPUTS

PREVIOUS RANK 2 DATA

DATA FROM RANK 1

DISABLING

OUT[0:16][N:P]

OUTPUTS

DATA FROM RANK 2

tCSU

tUW

tUOE

tCHU

tUOD

tUOT

Figure 28. Second Rank Update Cycle

Table 7. Second Rank Update Cycle

Parameter

Mnemonic

Setup Time

tCSU

Hold Time

tCHU

Output Enable Times

tUOE

Output Toggle Times

tUOT

Output Disable Times

tUOD

Update Pulse

tUW

Function

Chip select to update

Chip select from update

Update to output enable

Update to output reprogram

Update to output disabled

Width of update pulse

Conditions

TA = 25°C

VDD = 5 V

VCC = 3.3 V

Min Typ Max Unit

0

ns

ns

25

40

ns

25

40

ns

25 30

ns

15

ns

Rev. B | Page 14 of 40

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