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AD8151

33 × 17, 3.2 Gbps Digital Crosspoint Switch

Analog Devices 

AD8151

RE Input

Second Rank Read-Enable. Forcing this pin to logic low enables

the output drivers on the bidirectional D pins [6:0], entering

the readback mode of operation. By selecting an output address

with the A pins [4:0] and forcing RE to logic low, the 7-bit

data stored in the second rank latch for that output address is

written to the D pins [6:0]. Data should not be written to the

D pins [6:0] externally while in readback mode.

The RE and WE pins are not exclusive, and can be used at the

same time, but data should not be written to the D pins [6:0]

from external sources while in readback mode.

CS Input

Chip-Select. This pin must be forced to logic low to program or

receive data from the logic interface, with the exception of the

RESET pin, described in the next section. This pin has no

effect on the signal pairs and does not alter any of the stored

control data.

RESET Input

Global Output Disable Pin. Forcing the RESET pin to logic low

resets the enable bit, D6, in all 17 second rank latches,

regardless of the state of any of the other pins. This has the

effect of immediately disabling the 17 output signal pairs in the

matrix.

It is useful to momentarily hold RESET at a logic low state when

powering up the AD8151 in a system that has multiple output

signal pairs connected together. Failure to do this can result in

several signal outputs contending after power-up. The RESET

pin is not gated by the state of the chip-select pin, CS. It should

be noted that the RESET pin does not program the first rank,

which contains undefined data after power-up.

CONTROL INTERFACE TRANSLATORS

The AD8151 control interface has two supply pins, VDD and VSS.

The potential between the positive logic supply, VDD, and the

negative logic supply, VSS, must be at least 3 V and no more than

5 V. Regardless of supply, the logic threshold is approximately

1.6 V above VSS, allowing the interface to be used with most

CMOS and TTL logic drivers. The signal matrix supplies, VCC

and VEE, can be set independently of the voltage on VDD and VSS,

with the constraints that (VDD − VEE) ≤ 10 V. These constraints

allow operation of the control interface on 3 V or 5 V, while the

signal matrix is operated on 3.3 V or 5 V PECL or –3.3 V or

–5 V ECL.

Rev. B | Page 18 of 40

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