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AD8151

33 × 17, 3.2 Gbps Digital Crosspoint Switch

Analog Devices 

AD8151

To ensure proper operation, all outputs (including unused

output) must be pulled high using external pull-up networks to

a level within the output compliance range. If outputs from

multiple AD8151s are wired together, a single pull-up network

can be used for each output bus. The pull-up network should be

chosen to keep the output voltage levels within the output

compliance range at all times. Recommended pull-up networks

to produce PECL/ECL 100 kΩ and 10 kΩ compatible outputs

are shown in Figure 36. Alternatively, a separate supply can be

used to provide VCOM, making RCOM and DCOM unnecessary.

VCC

RCOM

VCC

DCOM

AD8151

RL

OUTyyN

OUTyyP

VCOM

RL

AD8151

RL

OUTyyN

OUTyyP

VCOM

RL

Figure 36. Output Pull-Up Networks for PECL/ECL: a) 100 kΩ and b) 10kΩ

The output levels are

VOH = VCOM

VOL = VCOM – IOUTRL

VSWING = VOH − VOL = IOUTRL

VCOM = VCC – IOUTRCOM (100 kΩ mode)

VCOM = VCC – V(DCOM) (10 kΩ mode)

The common-mode adjustment element (RCOM or DCOM) can be

omitted if the input range of the receiver includes the positive

supply voltage. The bypass capacitors reduce common-mode

perturbations by providing an ac short from the common nodes

(VCOM) to ground. When busing together the outputs of

multiple AD8151s or when running at high data rates, double

termination of its outputs is recommended to mitigate the

impact of reflections due to open transmission line stubs and

the lumped capacitance of the AD8151 output pins. A possible

connection is shown in Figure 37; the bypass capacitors provide

an ac short from the common nodes of the termination resistors

to ground. To maintain signal fidelity at high data rates, the

stubs connecting the output pins to the output transmission

lines or load resistors should be as short as possible.

VCC

RCOM

AD8151

RL

OUTyyN

OUTyyP

VCOM RL

AD8151

ZO

ZO

OUTyyN

OUTyyP

ZO

ZO

RL

RL

RECEIVER

Figure 37. Double Termination of AD8151 Outputs

In this case, the output levels are

VOH = VCOM – (¼)IOUTRL

VOL = VCOM – (¾)IOUTRL

VSWING = VOH – VOL = (½)IOUTRL

Output Current Set Pin (REF)

A simplified schematic of the reference circuit is shown in

Figure 38. A single external resistor connected between the REF

pin and VEE determines the output current for all output stages.

This feature allows a choice of pull-up networks and trans-

mission line characteristic impedances while still achieving a

nominal output swing of 800 mV. At low data rates, substantial

power savings can be achieved by using lower output swings

and higher load resistances.

AD8151

IOUT/20

VCC

1.2V

REF

RSET

VEE

Figure 38. Simplified Reference Circuit

The nominal output current is given by the following:

IOUT = 20⎜⎛ 1.2 V ⎟⎞

⎝ RSET ⎠

The minimum set resistor is RSET, MIN = 960 Ω resulting in

IOUT, MAX = 25 mA. The maximum set resistor is RSET, MAX = 4.8 kΩ

resulting in IOUT, MIN = 5 mA. Nominal 800 mV differential

output swing can be achieved in a 50 Ω load using RSET = 1.5 kΩ

(IOUT = 16 mA), or in a doubly terminated 75 Ω load using

RSET = 1.13 kΩ (IOUT = 21.3 mA). To minimize stray capacitance

and avoid the pickup of unwanted signals, the external set

resistor should be located close to the REF pin. Bypassing the

set resistor is not recommended.

Power Supplies

There are several options for the power supply voltages for the

AD8151, as there are two separate sections of the chip that

require power supplies. These are the control logic and the high

speed data paths. Depending on the system architecture, the

voltage levels of these supplies can vary.

Logic Supplies

The control (programming) logic is CMOS and is designed to

interface with any of the standard single-ended logic families

(CMOS or TTL). Its supply voltage pins are VDD (Pin 170, logic

positive) and VSS (Pin 152, logic ground). In all cases the logic

ground should be connected to the system digital ground. VDD

should be supplied at between 3.3 V to 5 V to match the supply

voltage of the logic family that is used to drive the logic inputs.

VDD should be bypassed to ground with a 0.1 μF ceramic capa-

citor. The absolute maximum voltage from VDD to VSS is 5.5 V.

Rev. B | Page 20 of 40

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