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AD8151

33 × 17, 3.2 Gbps Digital Crosspoint Switch

Analog Devices 

CIRCUIT DESCRIPTION

The AD8151 is a high speed 33 × 17 differential crosspoint

switch designed for data rates up to 3.2 Gbps per channel. The

AD8151 supports PECL-compatible input and output levels

when operated from a 5 V supply (VCC = 5 V, VEE = GND), or

ECL-compatible levels when operated from a –5 V supply

(VCC = GND, VEE = –5 V). To save power, the AD8151 can run

from a +3.3 V supply to interface with low voltage PECL

circuits or a –3.3 V supply to interface with low voltage ECL

circuits. The AD8151 utilizes differential current-mode outputs

with an individual disable control, which facilitates busing the

outputs of multiple AD8151s together to assemble larger switch

arrays. This feature also reduces system crosstalk and can

greatly reduce power dissipation in a large switch array. A single

external resistor programs the current for all enabled output

stages, allowing user control over output levels with different

output termination schemes and transmission line

characteristic impedances.

High Speed Data Inputs (INxxP, INxxN)

The AD8151 has 33 pairs of differential voltage-mode inputs.

The common-mode input range extends from the positive

supply voltage (VCC) down to include standard ECL or PECL

input levels (VCC – 2 V). The minimum differential input

voltage is 200 mV. Unused inputs may be connected directly to

any level within the allowed common-mode input range. A

simplified schematic of the input circuit is shown in Figure 33.

VCC

INxxP

INxxN

VEE

Figure 33. Simplified Input Circuit

To maintain signal fidelity at the high data rates supported by

the AD8151, the input transmission lines should be terminated

as close to the input pins as possible. The preferred input

termination structure depends primarily on the application and

the output circuit of the data source. Standard ECL components

have open emitter outputs that require pull-down resistors.

Three input termination networks suitable for this type of

source are shown in Figure 34. The characteristic impedance of

the transmission line is shown as ZO. The resistors, R1 and R2,

in the Thevenin termination are chosen to synthesize a VTT

source with an output resistance of ZO and an open-circuit

output voltage equal to VCC – 2 V. The load resistors (RL) in the

differential termination scheme are needed to bias the emitter

followers of the ECL source.

AD8151

VCC

VCC

VCC – 2V

ZO

ZO

ECL SOURCE ZO

INxxN

INxxP

ZO

VTT = VCC – 2V

(a)

ZO R1

ZO

R2

ECL SOURCE

R1

INxxN

INxxP

R2

VEE

(b)

VCC

RL

ECL SOURCE

ZO

ZO

RL

INxxN

2ZO

INxxP

VEE

(c)

Figure 34. AD8151 Input Termination from ECL/PECL Sources: (a) Parallel

Termination Using VTT Supply, (b) Thevenin Equivalent Termination,

and (c) Differential Termination

If the AD8151 is driven from a current-mode output stage such

as another AD8151, the input termination should be chosen to

accommodate that type of source, as explained in the following

section.

High speed Data Outputs (OUTyyP, OUTyyN)

The AD8151 has 17 pairs of differential current-mode outputs.

The output circuit, shown in Figure 35, is an open-collector

NPN current switch with resistor-programmable tail current

and output compliance extending from the positive supply

voltage (VCC) down to standard ECL or PECL output levels

(VCC − 2 V). The outputs can be disabled individually to permit

outputs from multiple AD8151s to be connected directly. Since

the output currents of multiple enabled output stages sum when

directly connected, care should be taken to ensure that the

output compliance limit is not exceeded at any time by disabling

the active output driver before enabling an inactive driver.

VCC

VCC – 2V

OUTyyP OUTyyN

DISABLE

IOUT

VEE

VEE

Figure 35. Simplified Output Circuit

Rev. B | Page 19 of 40

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