ADP3161 Ver la hoja de datos (PDF) - Analog Devices
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ADP3161 Datasheet PDF : 12 Pages
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ADP3161
The optimal implementation of voltage positioning, ADOPT,
will create an output impedance of the power converter that is
entirely resistive over the widest possible frequency range, includ-
ing dc, and equal to the maximum acceptable ESR of the output
capacitor array. With the resistive output impedance, the output
voltage will droop in proportion with the load current at any load
current slew rate; this ensures the optimal positioning and allows
the minimization of the output capacitor.
With an ideal current-mode-controlled converter, where the
average inductor current would respond without delay to the
command signal, the resistive output impedance could be achieved
by having a single-pole roll-off of the voltage gain of the voltage-
error amplifier. The pole frequency must coincide with the ESR
zero of the output capacitor. The ADP3161 uses constant frequency
current-mode control, which is known to have a nonideal, fre-
quency dependent command signal to inductor current transfer
function. The frequency dependence manifests in the form of a
pair of complex conjugate poles at one-half of the switching fre-
quency. A purely resistive output impedance could be achieved
by canceling the complex conjugate poles with zeros at the same
complex frequencies and adding a third pole equal to the ESR
zero of the output capacitor. Such a compensating network would
be quite complicated. Fortunately, in practice it is sufficient to
cancel the pair of complex conjugate poles with a single real zero
placed at one-half of the switching frequency. Although the end
result is not a perfectly resistive output impedance, the remaining
frequency dependence causes only a few percentage of deviation
from the ideal resistive response. The single-pole and single-
zero compensation can be easily implemented by terminating
the gm error amplifier with the parallel combination of a resistor
and a series RC network.
The first step in the design of the feedback loop compensation is
to determine the targeted output resistance, RE(MAX) of the power
converter using Equation 4. The compensation can then be
tailored to create that output impedance for the power converter,
and the quantity of output capacitors can be chosen to create a
net ESR that is less than or equal to RE(MAX).
The next step is to determine the total termination resistance of
the gm amplifier that will yield the correct output resistance:
RT
=
nI × RSENSE
gm × RE ( MAX ) × 2
=
25 × 4 mΩ
2.2 mmho × 2.9 mΩ × 2
= 7.84 kΩ
(22)
where nI is the division ratio from the output voltage signal of the
gm amplifier to the PWM comparator (CMP1), gm is the transcon-
ductance of the gm amplifier itself, and the factor of 2 is the result
of the two-phase configuration.
Once RT is known, the two resistors that make up the divider
from the REF pin to output of the gm amplifier (COMP pin)
must be calculated. The resistive divider introduces an offset to
the output of the gm amplifier that, when reflected back through
the gain of the gm stage, accurately positions the output voltage
near its allowed maximum at light load. Furthermore, the output
of the gm amplifier sets the current sense threshold voltage.
At no load, the current sense threshold is increased by the peak
of the ripple current in the inductor and reduced by the delay
between sensing when the current threshold has been reached
and when the high-side MOSFET actually turns off. These
two factors are combined with the inherent voltage at the output
of gm amplifier that commands a current sense threshold of
0 mV (VGNL0):
( ) VGNL
= VGNL0
+
I L( RIPPLE )
×
2
RCS
×
nI
− VIN
− VAVG
L
2 × tD × RCS × nI
VGNL
= 1V
+
5.7
A×
4 mΩ
2
× 25
− 5V − 1.78 V × 2 × 60 ns × 4 mΩ × 25 = 1.25V
1 µH
(23)
The output voltage at no load (VONL) can be calculated by start-
ing with the VID setting, adding in the positive offset (V+),
subtracting half the ripple voltage, and then subtracting the
dominant error terms:
VONL
= VVID
+V +
−
RE
× ∆IO
2
− VVID
×
2 kVID2
+
kRT
× VWIN
VVID
2
VONL
= 1.8 V
+
40 mV
−
2.9 mΩ × 2.6
2
A
–1.8 V ×
(0.007)2
+
0.02
×
83.5 mV 2
1.8 V
= 1.824 V
(24)
With these two terms calculated, the divider resistors (RA for
the upper, and RB for the lower) can be calculated. Assuming
that the internal resistance of the gm amplifier (ROGM) is 200 kΩ:
RB
=
VREF – VGNL
RT
VREF
− gm(VONL
− VVID )
RB
=
3V
− 1.25V
3V
− 2.2 mmho × (1.824 V
– 1.8 V )
(25)
7.84 kΩ
= 17.6 kΩ
Choosing the nearest 1% resistor value gives RB = 17.8 kΩ.
Finally, RA is calculated:
RA = 1 −
1
1
=
−1
1
1
−1−
1
= 15.1 kΩ
(26)
RT ROGM RB 7.84 kΩ 200 kΩ 17.8 kΩ
Again, choosing the nearest 1% resistor value gives RA = 15.0 kΩ.
The compensating capacitor can be calculated from the equation
COC
= COUT × RE
RT
−
π×
2
fOSC
× RT
COC
=
9 mF × 2.67 mΩ
7.84 kΩ
−
2
π × 400 kHz × 7.84
kΩ
=
2.86 nF
(27)
Choosing the nearest standard value yields 2.7 nF.
The resistance of the zero-setting resistor in series with the
compensating capacitor is
RZ
=
COC
2
×π×
fOSC
=
2.7 nF
2
× π × 400 kHz
= 590 kΩ
(28)
The nearest 2.7 standard 5% resistor value is 560 Ω.
–10–
REV. 0
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