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ADP3161

4-Bit Programmable 2-Phase Synchronous Buck Controller

Analog Devices 

ADP3161

VID3

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

Table I. Output Voltage vs. VID Code

VID2

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

VID1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

VID0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VOUT(NOM)

1.30 V

1.35 V

1.40 V

1.45 V

1.50 V

1.55 V

1.60 V

1.65 V

1.70 V

1.75 V

1.80 V

1.85 V

1.90 V

1.95 V

2.00 V

2.05 V

THEORY OF OPERATION

The ADP3161 combines a current-mode, fixed frequency PWM

controller with antiphase logic outputs in a controller for a two-

phase synchronous buck power converter. Two-phase operation

is important for switching the high currents required by high

performance microprocessors. Handling the high current in a

single-phase converter would place difficult requirements on the

power components such as inductor wire size, MOSFET ON-

resistance, and thermal dissipation. The ADP3161’s high-side

current sensing topology ensures that the load currents are

balanced in each phase, such that neither phase has to carry

more than half of the power. An additional benefit of high-

side current sensing over output current sensing is that the

average current through the sense resistor is reduced by the duty

cycle of the converter, allowing the use of a lower power, lower

cost resistor. The outputs of the ADP3161 are logic drivers only

and are not intended to directly drive external power MOS-

FETs. Instead, the ADP3161 should be paired with drivers such

as the ADP3412, ADP3413, or ADP3414. A system level block

diagram of a 2-phase power supply for high current CPUs is

shown in TPC 5.

The frequency of the ADP3161 is set by an external capacitor

connected to the CT pin. Each output phase of the ADP3161

operates at half of the frequency set by the CT pin. The error

amplifier and current sense comparator control the duty cycle of

the PWM outputs to maintain regulation. The maximum duty

cycle per phase is inherently limited to 50% because the PWM

outputs toggle in two-phase operation. While one phase is on,

the other phase is off. In no case can both outputs be high at the

same time.

Output Voltage Sensing

The output voltage is sensed at the FB pin allowing for remote

sensing. To maintain the accuracy of the remote sensing, the

GND pin should also be connected close to the load. A voltage

error amplifier (gm) amplifies the difference between the output

voltage and a programmable reference voltage. The reference

voltage is programmed between 1.3 V and 2.05 V by an inter-

nal 5-bit DAC, which reads the code at the voltage identification

(VID) pins. (Refer to Table I for the output voltage versus VID pin

code information.)

Active Voltage Positioning

The ADP3161 uses Analog Devices Optimal Positioning Technol-

ogy (ADOPT), a unique supplemental regulation technique that

uses active voltage positioning and provides optimal compensa-

tion for load transients. When implemented, ADOPT adjusts the

output voltage as a function of the load current, so that it is always

optimally positioned for a load transient. Standard (passive) volt-

age positioning has poor dynamic performance, rendering it

ineffective under the stringent repetitive transient conditions

required by high performance processors. ADOPT, however,

provides optimal bandwidth for transient response that yields

optimal load transient response with the minimum number of

output capacitors.

Reference Output

A 3.0 V reference is available on the ADP3161. This reference

is normally used to set the voltage positioning accurately using a

resistor divider to the COMP pin. In addition, the reference can be

used for other functions such as generating a regulated voltage

with an external amplifier. The reference is bypassed with a 1 nF

capacitor to ground. It is not intended to supply current to large

capacitive loads, and it should not be used to provide more than

1 mA of output current.

Cycle-by-Cycle Operation

During normal operation (when the output voltage is regulated),

the voltage-error amplifier and the current comparator are the

main control elements. The voltage at the CT pin of the oscilla-

tor ramps between 0 V and 3 V. When that voltage reaches 3 V,

the oscillator sets the driver logic, which sets PWM1 high. Dur-

ing the ON time of Phase 1, the driver IC turns on the high-side

MOSFET. The CS+ and CS– pins monitor the current through

the sense resistor that feeds both high-side MOSFETs. When

the voltage between the two pins exceeds the threshold level

set by the voltage error amplifier (gm), the driver logic is reset

and the PWM output goes low. This signals the driver IC to turn

off the high-side MOSFET and turn on the low-side MOSFET.

On the next cycle of the oscillator, the driver logic toggles and sets

PWM2 high. On each following cycle of the oscillator, the outputs

toggle between PWM1 and PWM2. In each case, the current

comparator resets the PWM output low when the current compara-

tor threshold is reached. As the load current increases, the output

voltage starts to decrease. This causes an increase in the output

of the gm amplifier, which in turn leads to an increase in the

current comparator threshold, thus programming more current to

be delivered to the output so that voltage regulation is maintained.

Active Current Sharing

The ADP3161 ensures current balance in the two phases by

actively sensing the current through a single sense resistor. During

one phase’s ON time, the current through the respective high-side

MOSFET and inductor is measured through the sense resistor

(R4 in TPC 6). When the comparator (CMP1 in the Functional

Block Diagram) threshold programmed by the gm amplifier is

reached, the high-side MOSFET turns off. In the next cycle the

ADP3161 switches to the second phase. The current is measured

with the same sense resistor and the same internal comparator,

ensuring accurate matching. This scheme is immune to imbalances

in the MOSFETs’ RDS(ON) and inductors’ parasitic resistances.

If for some reason one of the phases fails, the other phase will still

be limited to its maximum output current (one-half of the short

circuit current limit). If this is not sufficient to supply the load,

REV. 0

–5–

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