ADP3161 Ver la hoja de datos (PDF) - Analog Devices
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ADP3161 Datasheet PDF : 12 Pages
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ADP3161
for the power MOSFETs are VGS(TH) and RDS(ON). The mini-
mum gate drive voltage (the supply voltage to the ADP3412)
dictates whether standard threshold or logic-level threshold
MOSFETs must be used. Since VGATE < 8 V, logic-level threshold
MOSFETs (VGS(TH) < 2.5 V) are strongly recommended.
The maximum output current IO determines the RDS(ON) require-
ment for the power MOSFETs. When the ADP3161 is operating
in continuous mode, the simplifying assumption can be made
that in each phase one of the two MOSFETs is always conduct-
ing the average inductor current. For VIN = 5 V and VOUT =
1.8 V, the duty ratio of the high-side MOSFET is:
DHSF
= VOUT
VIN
= 36%
(11)
The duty ratio of the low-side (synchronous rectifier) MOSFET is:
DLSF = 1 – DHSF = 64%
(12)
The maximum rms current of the high-side MOSFET during
normal operation is:
IHSF ( MAX )
=
IO
2
DHSF
× 1 +
I2
L(RIPPLE )
3 × IO2
= 7.9 A
(13)
The maximum rms current of the low-side MOSFET during
normal operation is:
ILSF ( MAX ) = IHSF ( MAX )
DLSF = 10.5 A
DHSF
(14)
The RDS(ON) for each MOSFET can be derived from the allowable
dissipation. If 10% of the maximum output power is allowed for
MOSFET dissipation, the total dissipation in the four MOSFETs
of the two-phase converter will be:
PMOSFET(TOTAL ) = 0.1 ×VOUT × IO = 0.1 × 1.8V × 26 A = 4.7 W (15)
Allocating half of the total dissipation for the pair of high-side
MOSFETs and half for the pair of low-side MOSFETs, and
assuming that the resistive and switching losses of the high-side
MOSFET are equal, the required maximum MOSFET resis-
tances will be:
RDS(ON )HS( MAX )
=
PMOSFET(TOTAL )
8
×
I
2
HSF
(
MAX
)
=
4.7 W
8 × (7.9 A)2
= 9.4 mΩ
(16)
RDS(ON )LS ( MAX )
=
PMOSFET (TOTAL )
4
×
I
2
LSF
(
MAX
)
=
4.7 W
4 × (10.5 A)2
= 10.6 mΩ
(17)
An IRL3803 MOSFET from International Rectifier (RDS(ON) =
6 mΩ nominal, 9 mΩ worst case) is a good choice for both the
high-side and low-side. The high-side MOSFET dissipation is:
( ) PHSF =
RDS(ON )HS
×
I
2
HFS
(
MAX
)
+ VIN × IL(PK ) × QG × fSW
2 × IG
( ) + VIN × QRR × fSW
(18)
where the second term represents the turn-off loss of the MOSFET
and the third term represents the turn-on loss due to the stored
charge in the body diode of the low-side MOSFET. (In the
second term, QG is the gate charge to be removed from the gate
for turn-off and IG is the gate turn-off current. From the data
sheet, for the IRL3803 the value of QG is about 140 nC and
the peak gate drive current provided by the ADP3412 is about
1 A. In the third term, QRR is the charge stored in the body diode
of the low-side MOSFET at the valley of the inductor current.
The data sheet of the IRL3803 gives 450 nC for the stored charge
at 71 A. That value corresponds to a stored charge of 80 nC
at the valley of the inductor current. In both terms fSW is the
actual switching frequency of the MOSFETs, or 200 kHz. IL(PK)
is the peak current in the inductor, or 15.85 A.)
Substituting the above data in Equation 18, and using the worst-
case value for the MOSFET resistance, yields a conduction loss
of 0.56 W, a turn-off loss of 1.1 W, and a turn-on loss of 0.08 W.
Thus the worst-case total loss in a high-side MOSFET is 1.74 W.
The worst-case low-side MOSFET dissipation is:
PLSF
= RDS(ON )LS
×
I
2
LSF
(
MAX
)
= 9 mΩ × (10.5 A)2
= 1W
(19)
(Note that there are no switching losses in the low-side MOSFET.)
CIN Selection and Input Current di/dt Reduction
In continuous inductor-current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to VOUT/VIN and an amplitude of one-half of the
maximum output current. To prevent large voltage transients, a
low ESR input capacitor sized for the maximum rms current
must be used. The maximum rms capacitor current is given by:
IC(RMS )
=
IO
2
2 × DHSF − (2 × DHSF )2 =
26 A 2 × 0.36 – (2 × 0.36)2 = 5.8 A
(20)
2
Note that the capacitor manufacturer’s ripple current ratings are
often based on only 2000 hours of life. This makes it advisable to
further derate the capacitor, or to choose a capacitor rated at a
higher temperature than required. Several capacitors may be
placed in parallel to meet size or height requirements in the
design. In this example, the input capacitor bank is formed by
three 1000 µF, 16 V Rubycon capacitors.
The ripple voltage across the three paralleled capacitors is:
VC( RIPPLE )
=
IO
n
×
ESRC
nC
+
nC
DHSF
× CIN ×
fSW
=
26 A
2
×
24 mΩ
3
+
3
× 1000
0.36
µF ×
200
kHz
=
112
mV
(21)
To reduce the input-current di/dt to below the recommended
maximum of 0.1 A/µs, an additional small inductor (L > 1 µH
@ 15 A) should be inserted between the converter and the sup-
ply bus. That inductor also acts as a filter between the converter
and the primary power source.
Feedback Loop Compensation Design for ADOPT
Optimized compensation of the ADP3161 allows the best pos-
sible containment of the peak-to-peak output voltage deviation.
Any practical switching power converter is inherently limited by
the inductor in its output current slew rate to a value much less
than the slew rate of the load. Therefore, any sudden change of
load current will initially flow through the output capacitors,
and assuming that the capacitance of the output capacitor is
larger than the critical value defined by Equation 5, this will
produce a peak output voltage deviation equal to the ESR of the
output capacitor times the load current change.
REV. 0
–9–
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