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CS8920A

Crystal LAN ISA Plug-and-Play Ethernet Controller

Cirrus Logic 

CS8920A

3.0 FUNCTIONAL DESCRIPTION

3.1 Overview

During normal operation, the CS8920A performs

two basic functions: Ethernet packet transmis-

sion and reception. Before transmission or

reception is possible, the CS8920A must be con-

figured.

Configuration

The CS8920A must be configured for packet

transmission and reception at power-up or reset.

Various parameters must be written into its inter-

nal Configuration and Control registers such as

Memory Base Address; Ethernet Physical Ad-

dress; what frame types to receive; and which

media interface to use. Configuration data can

either be written to the CS8920A by the host

(across the ISA bus), or loaded automatically

from an external EEPROM. Operation can begin

after configuration is complete.

Sections 3.1 and 3.3 describe the configuration

process in detail. Section 4.4 provides a detailed

description of the bits in the Configuration and

Control Registers.

Packet Transmission

Packet transmission occurs in two phases. In the

first phase, the host moves the Ethernet frame

into the CS8920A’s buffer memory. The first

phase begins with the host issuing a Transmit

Command. This informs the CS8920A that a

frame is to be transmitted and tells the chip

when (i.e. after 5, 381, or 1021 bytes have been

transferred or after the full frame has been trans-

ferred to the CS8920A) and how the frame

should be sent (i.e. with or without CRC, with or

without pad bits, etc.). The host follows the

Transmit Command with the Transmit Length,

indicating how much buffer space is required.

When buffer space is available, the host writes

the Ethernet frame into the CS8920A’s internal

14

memory, either as a Memory or I/O space opera-

tion.

In the second phase of packet transmission, the

CS8920A converts the frame into an Ethernet

packet, then transmits it onto the network. The

second phase begins with the CS8920A transmit-

ting the preamble and Start-of-Frame delimiter

as soon as the proper number of bytes have been

transferred into its transmit buffer (5, 381, 1021

bytes or full frame, depending on configuration).

The preamble and Start-of-Frame are followed

by the Destination Address, Source Address,

Length field and LLC data (all supplied by the

host). If the frame is less than 64 bytes, includ-

ing CRC, the CS8920A adds pad bits if

configured to do so. Finally, the CS8920A ap-

pends the proper 32-bit CRC value.

Section 5.8 provides a detailed description of

packet transmission.

Packet Reception

Like packet transmission, packet reception oc-

curs in two phases. In the first phase, the

CS8920A receives an Ethernet packet and stores

it in on-chip memory. The first phase begins

with the receive frame passing through the ana-

log front end and Manchester decoder where

Manchester data is converted to NRZ data. Next,

the preamble and Start-of-Frame delimiter are

stripped off and the receive frame is sent through

the address filter. If the frame’s Destination Ad-

dress matches the criteria programmed into the

address filter, the packet is stored in the

CS8920A’s internal memory. The CS8920A then

checks the CRC, and depending on the configu-

ration, informs the processor that a frame has

been received.

In the second phase, the host transfers the re-

ceive frame across the ISA bus and into host

memory. Receive frames can be transferred as

Memory space operations, I/O space operations,

or as DMA operations using host DMA. In addi-

DS238PP2

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