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CS8920A

Crystal LAN ISA Plug-and-Play Ethernet Controller

Cirrus Logic 

CS8920A

than approximately 2.5 V and the crystal oscilla-

tor has stabilized.

Power-Down Reset: If the supply voltage drops

below approximately 2.5 V, there is a chip-wide

reset. The CS8920A comes out of reset once the

power supply returns to a level greater than ap-

proximately 2.5 V and the crystal oscillator has

stabilized.

EEreset: There is a chip-wide reset if the

CS8920A detects an EEPROM checksum error.

(see Section 3.1).

Software Initiated Reset: There is a chip-wide

reset whenever the RESET bit (Register 15,

SelfCTL, Bit 6) is set. The Plug and Play card

select number, Plug and Play Rd Data port,

PnP_disable bit, IO base address register, mem-

ory base address register, interrupt register, and

DMA register are preserved. The digital logic is

reset, but the analog circuits are not.

Hardware (HW) Standby or Suspend: The

CS8920A goes though a chip-wide reset when-

ever it enters or exits either HW Standby mode

or HW Suspend mode (see Section 3.8 for more

information about HW Standby and Suspend).

Software (SW) Suspend: Whenever the

CS8920A enters SW Suspend mode, all registers

and circuits are reset except for the ISA I/O Base

Address register (located at PacketPage base +

0360h) and the SelfCTL register (Register 15).

Upon exit, there is a chip-wide reset (see Section

3.8 for more information about SW Suspend).

PnP Initiated Reset: Writing a one (setting

bit[0]) to the Plug and Play Config Control reg-

ister (address 0x02) causes all digital registers to

be reset, including the CS8920A’s Card select

Number and Plug and Play Read Data Port ad-

dress. At the end of the reset, the CS8920A will

attempt to read configuration information from

EEPROM. The analog circuits are not reset.

DS238PP2

Magic Packet Frame Generated Reset: In power

down mode, with WakeupEn=1, the CS8920A

won’t reset completely unless the reset signal it

detects is followed by 6 MEMR cycles. The

Magic Packet frame generated reset ensures the

CS8920A resets only when it receives a true

power up reset signal.

3.3.2 Allowing Time for Reset Operation

After a reset, the CS8920A goes through a self

configuration. This includes calibrating on-chip

analog circuitry, and reading EEPROM for valid-

ity and configuration. Time required for the reset

calibration is typically 10 ms. Software drivers

should not access registers internal to the

CS8920A during this time. When calibration is

done, bit INITD in the Self Status Register (reg-

ister 16) is set indicating that initialization is

complete, and the SIBUSY bit in the same regis-

ter is cleared indicating the EEPROM is no

longer being read or programmed.

3.3.3 Bus Reset Considerations

The CS8920A reads 3000h from IObase+0Ah

after the reset, until the software writes a non-

zero value at IObase+0Ah. The 3000h address

can be used as part of the CS8920A signature

when the system scans for the CS8920A. See

Section 4.12, I/O Space Operation.

After a reset, the ISA bus outputs IRQx and

DRQx are tri-stated, thus avoiding any interrupt

or DMA channel conflicts on the ISA bus at

power-up time.

Initialization

After each reset (except EEPROM Reset), the

CS8920A checks the sense of the EEDI pin to

see if an external EEPROM is present. If EEDI

is high, an EEPROM is present and the

CS8920A automatically loads the configuration

data stored in the EEPROM into its internal reg-

isters (see next section). If EEDI is low, an

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