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DM9102H

Single Chip Fast Ethernet NIC Controller

Davicom Semiconductor, Inc. 

DM9102H

Single Chip Fast Ethernet NIC Controller

Content

1. General Description........................................................................................................... 0

2. Block Diagram.................................................................................................................... 0

3. Features.............................................................................................................................. 1

4. Pin Configuration: 128 pin LQFP...................................................................................... 2

5. Pin Description .................................................................................................................. 3

5.1 PCI Bus Interface Signals ............................................................................................................................. 3

5.2 Boot ROM and EEPROM Interfaces ............................................................................................................. 4

5.3 LED Pins ....................................................................................................................................................... 5

5.4 Network Interface .......................................................................................................................................... 5

5.5 Miscellaneous Pins ....................................................................................................................................... 6

5.6 Power Pins .................................................................................................................................................... 7

5.7 NC Pins ......................................................................................................................................................... 7

6. Register Definition............................................................................................................. 8

6.1 PCI Configuration Registers.......................................................................................................................... 8

6.1.1 Identification ID (xxxxxx00H - PCIID) .................................................................................................... 9

6.1.2 Command & Status (xxxxxx04H - PCICS)............................................................................................. 9

6.1.3 Revision ID (xxxxxx08H - PCIRV) ....................................................................................................... 11

6.1.4 Miscellaneous Function (xxxxxx0cH - PCILT) ..................................................................................... 12

6.1.5 I/O Base Address (xxxxxx10H - PCIIO)............................................................................................... 12

6.1.6 Memory Mapped Base Address (xxxxxx14H - PCIMEM).................................................................... 13

6.1.7 Subsystem Identification (xxxxxx2cH - PCISID).................................................................................. 13

6.1.8 Expansion ROM Base Address (xxxxxx30 - PCIROM) ....................................................................... 14

6.1.9 Capabilities Pointer (xxxxxx34H - Cap _Ptr) ....................................................................................... 14

6.1.10 Interrupt & Latency Configuration (xxxxxx3cH - PCIINT) .................................................................. 15

6.1.11 Device Specific Configuration Register (xxxxxx40H- PCIUSR)......................................................... 15

6.1.12 Power Management Register (xxxxxx50H~PCIPMR) ....................................................................... 16

6.1.13 Power Management Control/Status (xxxxxx54H~PMCSR)............................................................... 17

6.2 Control and Status Registers (CR).............................................................................................................. 18

6.2.1 System Control Register (CR0) ........................................................................................................... 19

6.2.2 Transmit Descriptor Poll Demand (CR1) ............................................................................................. 19

6.2.3 Receive Descriptor Poll Demand (CR2) .............................................................................................. 19

6.2.4 Receive Descriptor Base Address (CR3) ............................................................................................ 20

6.2.5 Transmit Descriptor Base Address (CR4)............................................................................................ 20

6.2.6 Network Status Report Register (CR5)................................................................................................ 20

6.2.7 Network Operation Mode Register (CR6)............................................................................................ 22

6.2.8 Interrupt Mask Register (CR7)............................................................................................................. 24

6.2.9 Statistical Counter Register (CR8)....................................................................................................... 26

6.2.10 Management Access Register (CR9) ................................................................................................ 26

6.2.11 PHY Status Register (CR12).............................................................................................................. 28

Final

Version: DM9102H-12-DS-F01

February 15, 2008

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