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DM9102H

Single Chip Fast Ethernet NIC Controller

Davicom Semiconductor, Inc. 

27

STOP#

30

PERR#

31

SERR#

33

PAR

2,20,34,48

121,122,123,124,126,127,

128,1,6,7,10,11,13,14,16,

17,38,39,40,41,43,44,47,

49,50,51,54,55,56,57,59,

60

C/BE3#

C/BE2#

C/BE1#

C/BE0#

AD31~AD0

5.2 Boot ROM and EEPROM Interfaces

Pin No.

Pin Name

128LQFP

62

MD0/EEDI

63,64,65,66,67,68,69

72

78

79

MD1~MD7

BPCS#/EECS

EEDO

EECK

Final

Version: DM9102H-12-DS-F01

February 15, 2008

DM9102H

Single Chip Fast Ethernet NIC Controller

I/O Stop

This signal is asserted low by the target device to request the

master device to stop the current transaction.

I/O Parity Error

The DM9102H as a master or slave will assert this signal low

to indicate a parity error on any incoming data.

I/O System Error

This signal is asserted low when address parity is detected

with enabled PCICS bit31 (detected parity error.) The system

error asserts two clock cycles after the falling address if an

address parity error is detected.

I/O Parity

This signal indicates even parity across AD0~AD31 and

C/BE0#~C/BE3# including the PAR pin. This signal is an

output for the master and an input for the slave device. It is

stable and valid one clock after the address phase.

I/O Bus Command/Byte Enable

During the address phase, these signals define the bus

command or the type of bus transaction that will take place.

During the data phase these pins indicate which byte lanes

contain valid data. C/BE0# applies to bit7-0 and C/BE3#

applies to bit31-24.

I/O Address & Data or Boot ROM Address

These are multiplexed address and data bus signals. As a

bus master, the DM9102H will drive address during the first

bus phase. During subsequent phases, the DM9102H will

either read or write data expecting the target to increment its

address pointer. As a target, the DM9102H will decode each

address on the bus and respond if it is the target being

addressed.

AD17~AD0 can also be used as boot ROM address

MA17~MA0 when the boot ROM is accessed.

I/O

Description

I Boot ROM Data Input/EEPROM Data In

This is a multiplexed pin used by EEDI and MD0.

When boot ROM is selected, it acts as boot ROM data input,

otherwise the DM9102H will read the contents of EEPROM

serially through this pin.

I Boot ROM Data Input Bus

MD1, MD2 and MD7 can be used as strap pins.

See straps pin table for description.

O Boot ROM (active low) or EEPROM Chip Selection.

O EEPROM Data Out

This pin is used serially to write op-codes, addresses and

data into the EEPROM.

O EEPROM Serial Clock

This pin is used as the clock for the EEPROM data transfer.

4

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