DM9102H Ver la hoja de datos (PDF) - Davicom Semiconductor, Inc.
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DM9102H Datasheet PDF : 77 Pages
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DM9102H
Single Chip Fast Ethernet NIC Controller
6.2.12 Sample Frame Access Register (CR13) ................................................................................................... 29
6.2.13 Sample Frame Data Register (CR14)....................................................................................................... 29
6.2.14 Watchdog and Jabber Timer Register (CR15)................................................................................... 29
6.3 PHY Management Register Set .................................................................................................................. 30
6.3.1 Basic Mode Control Register (BMCR) – 0........................................................................................... 31
6.3.2 Basic Mode Status Register (BMSR) – 1............................................................................................. 32
6.3.3 PHY Identifier Register #1 (PHYIDR1) – 2 .......................................................................................... 33
6.3.4 PHY Identifier Register #2 (PHYIDR2) - 3 ........................................................................................... 33
6.3.5 Auto-negotiation Advertisement Register (ANAR) – 4 ......................................................................... 33
6.3.6 Auto-negotiation Link Partner Ability Register (ANLPAR) – 5.............................................................. 35
6.3.7 Auto-negotiation Expansion Register (ANER) – 6 ............................................................................... 36
6.3.8 DAVICOM Specified Configuration Register (DSCR) – 10H ............................................................... 36
6.3.9 DAVICOM Specified Configuration and Status Register (DSCSR) – 11H ........................................... 37
6.3.10 10BASE-T Configuration/Status (10BTCSRCSR) – 12H .................................................................. 38
6.3.11 Power down Control Register (PWDOR) – 13H ................................................................................ 38
6.3.12 (Specified config) Register – 20......................................................................................................... 39
6.3.13 Power Saving Control Register (PSCR) – 1DH................................................................................. 40
7. Functional Description.................................................................................................... 41
7.1 System Buffer Management........................................................................................................................ 41
7.1.1 Overview .............................................................................................................................................. 41
7.1.2 Data Structure and Descriptor List....................................................................................................... 41
7.1.3 Buffer Management -- Chain Structure Method................................................................................... 41
7.1.4 Descriptor List: Buffer Descriptor Format ............................................................................................ 42
7.1.5 Setup Frame ........................................................................................................................................ 46
7.2 Initialization Procedure................................................................................................................................ 48
7.2.1 Data Buffer Processing Algorithm........................................................................................................ 48
7.2.2 Receive Data Buffer Processing.......................................................................................................... 48
7.2.3 Transmit Data Buffer Processing ......................................................................................................... 49
7.3 Network Function ........................................................................................................................................ 50
7.3.1 Overview .............................................................................................................................................. 50
7.3.2 Receive Process and State Machine ................................................................................................... 50
7.3.3 Transmit Process and State Machine .................................................................................................. 50
7.3.4 Physical Layer Overview ..................................................................................................................... 50
7.4 Serial Management Interface ...................................................................................................................... 51
7.4.1 Management Interface - Read Frame Structure .................................................................................. 51
7.4.2 Management Interface - Write Frame Structure .................................................................................. 51
7.5 Power Management .................................................................................................................................... 52
7.5.1 Overview .............................................................................................................................................. 52
7.5.2 PCI Function Power Management States............................................................................................ 52
7.5.3 The Power Management Operation..................................................................................................... 52
7.6 Sample Frame Programming Guide: .......................................................................................................... 54
7.7 EEPROM Overview..................................................................................................................................... 55
7.7.1 Subsystem ID Block............................................................................................................................. 55
7.7.2Vendor ID .............................................................................................................................................. 55
7.7.3 Word Offset (04): Auto_ Load_ Control ............................................................................................... 55
7.7.4 Word Offset (04): New_ Capabilities_ Enable ..................................................................................... 55
7.7.5 Word Offset (07): PMC ........................................................................................................................ 55
7.7.6 Word Offset (07): Control..................................................................................................................... 55
Final
Version: DM9102H-12-DS-F01
February 15, 2008
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