IDT72205LB Ver la hoja de datos (PDF) - Integrated Device Technology

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IDT72205LB

CMOS SyncFIFO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18

Integrated Device Technology 

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™

256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18

WCLK

D0 - D17

WEN

RCLK

EF

t DS

D0 (first valid write)

D1

t ENS

tSKEW2

(1)

tFRL

t REF

MILITARY AND COMMERCIAL TEMPERATURE RANGES

D2

D3

D4

REN

Q0 - Q17

OE

tA

t OLZ

t OE

tA

D0

D1

2766 drw 10

NOTES:

1. When tSKEW2 ≥ minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2 * tCLK +

tSKEW2 or tCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW).

2. The first word is available the cycle after EF goes HIGH, always.

Figure 8. First Data Word Latency after Reset with Simultaneous Read and Write

5.16

12

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