IDT72205LB Ver la hoja de datos (PDF) - Integrated Device Technology

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IDT72205LB

CMOS SyncFIFO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18

Integrated Device Technology 

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™

256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18

MILITARY AND COMMERCIAL TEMPERATURE RANGES

WCLK

D0 - D17

NO WRITE

(1)

t SKEW1

t DS

DATA WRITE

NO WRITE

(1)

tSKEW1

t DS

DATA WRITE

t WFF

t WFF

FF

t WFF

WEN

RCLK

REN

t ENS

t ENH

t ENS

t ENH

OE

LOW

tA

tA

Q0 - Q17 DATA IN OUTPUT REGISTER

DATA READ

NEXT DATA READ

2766 drw 11

Figure 9. Full Flag Timing

NOTE:

1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the

time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.

5.16

13

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