IDT72205LB Ver la hoja de datos (PDF) - Integrated Device Technology

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IDT72205LB

CMOS SyncFIFO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18

Integrated Device Technology 

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™

256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18

MILITARY AND COMMERCIAL TEMPERATURE RANGES

WCLK

tDS

tDS

D0 - D17

tENS

WEN

RCLK

DATA WRITE 1

tENH

tSKEW2

tFRL (1)

EF

tENS

DATA WRITE 2

tENH

tSKEW2

(1)

tFRL

tREF

tREF

REN

OE

LOW

Q0 - Q17

tA

DATA IN OUTPUT REGISTER

DATA READ

2766 drw 12

Figure 10. Empty Flag Timing

NOTE:

1. When tSKEW2 ≥ minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2 * tCLK + tSKEW2.

or tCLK + tSKEW2. The Latency Timing apply only at the Empty Boundary (EF = LOW).

5.16

14

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