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IDT72205LB

CMOS SyncFIFO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18

Integrated Device Technology 

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™

256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18

MILITARY AND COMMERCIAL TEMPERATURE RANGES

WIDTH EXPANSION CONFIGURATION

Word width may be increased simply by connecting to-

gether the control signals of multiple devices. Status flags can

be detected from any one device. The exceptions are the

Empty Flag and Full Flag. Because of variations in skew

between RCLK and WCLK, it is possible for flag assertion and

deassertion to vary by one cycle between FIFOs. To avoid

problems the user must create composite flags by ANDing the

Empty Flags of every FIFO, and separately ANDing all Full

Flags. Figure 21 demonstrates a 36-word width by using two

IDT72205B/72215B/72225B/72235B/72245Bs. Any word

width can be attained by adding additional IDT72205B/72215B/

72225B/72235B/72245Bs. Please see the Application Note

AN-83.

RESET (RS)

RESET (RS)

DATA IN (D) 36

18

WRITE CLOCK (WCLK)

WRITE ENABLE (WEN)

LOAD (LD)

PROGRAMMABLE (PAE)

HALF FULL FLAG (HF)

FULL FLAG (FF)

18

72205LB/

72215LB/

72225LB/

72235LB/

72245LB

FF

EF

72205LB/

72215LB/

72225LB/

72235LB/

72245LB

FF

EF

18

FIRST LOAD (FL)

WRITE EXPANSION IN (WXI)

READ EXPANSION IN (RXI)

READ CLOCK (RCLK)

READ ENABLE (REN)

OUTPUT ENABLE (OE)

PROGRAMMABLE (PAF)

EMPTY FLAG (EF)

18

DATA OUT (Q) 36

2766 drw 23

NOTE:

1. Do not connect any output control signals directly together.

Figure 21. Block Diagram of 256 x 36/512 x 36/1024 x 36/2048 x 36/4096 x 36 Synchronous FIFO Memory Used in a

Width Expansion Configuration

DEPTH EXPANSION CONFIGURATION

(WITH PROGRAMMABLE FLAGS)

The IDT72205LB/72215LB/72225LB/72235LB/72245LB can

easily be adapted to applications requiring more than 256/

512/1024/2048/4096 words of buffering. Figure 22 shows

Depth Expansion using three IDT72205LB/72215LB/72225LB/

72235LB/72245LBs. Maximum depth is limited only by signal

loading. Follow these steps:

1. The first device must be designated by grounding the

First Load (FL) control input.

2. All other devices must have FL in the HIGH state.

3. The Write Expansion Out (WXO) pin of each device

must be tied to the Write Expansion In (WXI) pin of

the next device. See Figure 24.

4. The Read Expansion Out (RXO) pin of each device

must be tied to the Read Expansion In (RXI) pin of

the next device. See Figure 24.

5. All Load (LD) pins are tied together.

6. The Half-Full Flag (HF) is not available in the Depth

Expansion Configuration.

7. EF, FF, PAE, and PAF are created with composite

flags by ORing together every respective flags for

monitoring. The composite PAE and PAF flags are not

precise.

5.16

19

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