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IDT72205LB

CMOS SyncFIFO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18

Integrated Device Technology 

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™

256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18

MILITARY AND COMMERCIAL TEMPERATURE RANGES

WCLK

WEN

tCLKH

tCLKL

tENS

tENH

PAE

tPAE

n + 1 words

in FIFO

tPAE

RCLK

tENS

REN

NOTE:

1. PAE is offset = n. Number of data words written into FIFO already = n.

Figure 13. Programmable Almost Empty Flag Timing

n words in FIFO

2766 drw 15

WCLK

WEN

tCLKH

tCLKL

(1)

tENS

tENH

PAF

tPAF

Full – m words

in FIFO(2)

Full – m + 1 words

in FIFO(3)

tPAF

RCLK

tENS

REN

2766 drw 16

NOTES:

1. PAF offset = m. Number of data words written into FIFO already = 256 - m + 1 for the IDT72205B, 512 - m + 1 for the IDT72215B, 1024 - m + 1 for the

IDT72225B, 2048 – m + 1 for the IDT72235B and 4096 – m +1 for the IDT72245B.

2. 256 - m words in IDT72205B, 512 - m words in IDT72215B, 1024 - m words in IDT72225B, 2048 – m words in IDT72235B and 4096 – m words in IDT72245B.

3. 256 - m + 1 words in IDT72205B, 512 - m + 1 words in IDT72215B, 1024 - m + 1 words in IDT72225B, 2048 – m + 1 words in IDT72235B and 4096 – m

+ 1 words in IDT72245B.

Figure 14. Programmable Almost-Full Flag Timing

5.16

16

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