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LAN91C110

FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications

SMSC -> Microchip 

MII SELECT - Used to select the network interface port. When set, the LAN91C110 will use its MII port and interface a

PHY device at the nibble rate. This bit must always be set for proper chip function.

NO WAIT - When set, does not request additional wait states. An exception to this are accesses to the Data Register if not

ready for a transfer. When clear, negates ARDY for two to three clocks on any cycle to the LAN91C110.

FULL STEP - Reserved

AUI SELECT - This bit is a general purpose output port. Its value drives pin AUISEL and can be used as a general

purpose non-volatile configuration pin. Defaults low.

Reserved - Must be 0.

INT SEL1-0 - Used to select interrupt pin. The bits must remain 00 for the interrupt pin to be asserted for interrupt

indication. All other bit combinations are undefined.

BANK 1

OFFSET

2

NAME

BASE ADDRESS REGISTER

TYPE

READ/WRITE

SYMBOL

BAR

This register holds the I/O address decode option chosen for the LAN91C110. Is not usually modified during run-time.

HIGH

A15

A14

A13

A9

A8

A7

A6

A5

BYTE

0

0

0

1

1

0

0

0

LOW

Reserved

1

BYTE

0

0

0

0

0

0

0

1

A15 - A13 and A9 - A5 - These bits are compared against the I/O address on the bus to determine the IOBASE for the

LAN91C110‘s registers. The 64k I/O space is fully decoded by the LAN91C110 down to a 16 location space, therefore the

unspecified address lines A4, A10, A11 and A12 must be all zeros.

The I/O base decode defaults to 300h (namely, the high byte defaults to 18h).

Reserved - Must be 0.

SMSC LAN91C110 Rev. B

Page 24

DATASHEET

Revision 1.0 (11-04-08)

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