MX98741 Ver la hoja de datos (PDF) - Macronix International
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Lista de partido
MX98741 Datasheet PDF : 34 Pages
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PAD #
47
Name
PARTLNK
46
JBFLO
45
PTSCEN
44
PIDIS
48
ISO
43
RDXWR
41
REGLTCH
40
REGCK
P/N:PM0342
MX98741
I/O
O, TTL
O, TTL
I/O, TTL
I/O, TTL
O, TTL
I, TTL
I/O, TTL
I, TTL
D. Register Access Pins, 8 pins
Description
Partition/Link Status. This pin shows the status of internal register
#18 in round-robin fashion starting at port 0 partition status and
ending at port7 Link Status after REGLTCH is deasserted.
Jabber/Buffer Status. This pin shows the status of internal register
#19 in round-robin fashion starting at port 0 Jabber Status and
ending at port 7 Elastic Buffer Over/Underflow Status after
REGLTCH is deasserted.
Port/Scrambler Enable. If RDXWR is high, each port's enable/dis-
able status (register #17) will be displayed at the rising edge of
REGCK in round-robin fashion starting at port 0 Port 0 Enable sta-
tus and ending at port 7 Scrambler Enable status after REGLTCH
is deasserted. If RDXWR is low, 16-bit data can be written into the
XRC at the rising edge of REGCK in round-robin fashion starting
at port 0 Port Enable Signal and ending at port 7 Scrambler enable
after REGLTCH is asserted high. Internally pull-up.
Partition/Isolation Disable. If RDXWR is high, each port's partition/
Isolation Disable status will be displayed at the rising edge of
REGCK in round-robin fashion starting at port 0 partition disable
status and ending at port7 Isolation Disable status after REGLTCH
is deasserted. If RDXWR is low, 16-bit data can be written into the
XRC at the rising edge of REGCK in round-robin fashion starting
at port 0 partition disable status and ending at port 7 Isolation dis-
able status after REGLTCH is asserted high. Internally pull-down.
Isolation. Active High. Each port's isolation status will be displayed
at the rising edge of REGCK in round-robin fashion starting at port0
after REGLTCH is deasserted.
Read/Write. High indicates "Read" mode; register is being read
out. REGLTCH is output. Low indicates "Write" mode; control reg-
isters are being written and REGLTCH is input. When RDXWR is
programmed to "Write" Mode, internal "Read" status machine will
be reset immediately.
Register Latch. An output if RDXWR is high; an input if RDXWR is
low. At the rising edge of REGCK, PARTLNK, JBFLO, PTSCEN,
PIDIS, ISO display bit 0 status of corresponding registers, at the
rising edge of next REGCK, bit 1 status is displayed, etc. After bit
15 is displayed, REGLTCH is asserted at the rising edge of next
REGCK. Note : Both Data and REGLTCH are driven at the falling
edge of REGCK inside the XRC. To make sure the data setup
time, it is strongly recommended that the frequency of REGCK is
below 12.5 MHz. Internally pull-down.
Register Clock. A clock used as reference to display various sta-
tus of each port or to latch control information inside XRC. The
recommended clock's frequency is below 12.5MHz.
REV. 1.4, NOV. 07, 1996
5
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