MX98741 Ver la hoja de datos (PDF) - Macronix International
Número de pieza
componentes Descripción
Lista de partido
MX98741 Datasheet PDF : 34 Pages
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MX98741
PAD #
141
Name
RXER
143
RXCLK
137-140
RXD[0:3]
I/O
O, EXP
O, MII
O, MII
142
COL
154
MDC
O, EXP
I, TTL
G. Power/Ground/Test/Loopback, 39 pins
206
TEST
I, TTL
207
TSEL
I, TTL
1,14,22,
38,42,49
52,53,71,
77,101
104,105,
124,136,
155,156,
165,166,
173,182,
202,208
28,29,
39,64,
65,82,
89,95,
133,144,
157,176,
195,196
GND
VCC
Description
Receive Error. Synchronous to RXCLK's rising edge. While RXDV
is asserted, i.e. a frame is being received, this signal is asserted if
any coding error is detected. High-impedence after reset.
Receive Clock MII. 25 MHz continuous clock that provides the
timing reference for the transfer of the RXDV, RXD and RXER sig-
nals. High-impedance after reset.
Receive Data MII. Synchronous to RXCLK's rising edge. For each
RXCLK period in which RXDV is asserted, RXD[3:0] should be
latched by the MAC. While RXDV is deasserted, RXD[3:0] are the
nibbles 5B/4B decoded from RDAT[4:0]. RXD3 is the Most Signifi-
cant Bit. High-impedance after reset.
Collision MII. This signal is asserted if both the receiving media
and TXEN are active. High-impedance after reset.
Management Data Clock. The timing reference for MDIO.
The minumum high and low times are 200 ns each. No limitation
on the maximum high and low time.
Test. Industrial test pin. Set to 0 or left unconnected for normal
operation. When programmed to logic 1, XRC is in test mode.
Internal Pulldown.
Test Mode Select. When TEST is high and TSEL is low, XRC is in
"Real Time Counter" Mode; when TEST is high and TSEL is high,
XRC is in "Test Mode Counter" mode. Internally pull down.
Ground.
5V Power Supply.
P/N:PM0342
REV. 1.4, NOV. 07, 1996
8
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