MX98741 Ver la hoja de datos (PDF) - Macronix International

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MX98741

XRC 100 BASE-TX/FX REPEATER CONTROLLER

Macronix International 

MX98741

F. Media Independent Interface (MII, Continued)

PAD #

Name

I/O

Description

125

TXENB

I, TTL Transmit Enable MII B. Synchronous to the TXCLK's rising edge. It

is asserted by the MAC with the first nibble of the preamble and

remains asserted while all nibbles to be transmitted are presented.

126-129

TXDB[0:3]

I, TTL Transmit Data MII B. Synchronous to the TXCLK's rising edge. For

each TXCLK period in which TXENB is asserted, TXDB[3:0] are

also driven by the MAC. While TXENB is de-asserted, the value of

TXDB[3:0] is ignored. TXDB3 is the Most Significant Bit.

130

TXERB

I, TTL Transmit Error MII B. Synchronousto the TXCLK's rising edge.When

TXERB is asserted for one or more TXCLK period while TXENB is

also asserted, one or more "HALT" symbols will present at TDAT4_0.

131

RXDVB

O, TTL Receive Data Valid MII B. Synchronous to RXCLK's rising edge.

This signal remains asserted through the whole frame, starting with

the start-of-frame delimiter and excluding any end-of-frame

deliminter. High impedance after reset.

132

CRSB

O, TTL Carrier Sense MII B. In TX mode, synchronous to RXCLK. This

pin is asserted when (1) the receiving medium is not idle, or (2) the

transmitting medium is not idle in the half-duplex mode. High im-

pedance after reset.

145

TXENC

I, TTL Transmit Enable MII C. Synchronous to the TXCLK's rising edge. It

is asserted by the MAC with the first nibble of the preamble and

remains asserted while all nibbles to be transmitted are presented.

146-149

TXDC[0:3]

I, TTL Transmit Data MII C. Synchronous to the TXCLK's rising edge. For

each TXCLK period in which TXENC is asserted, TXDC[3:0] are

also driven by the MAC. While TXENC is de-asserted, the value of

TXDC[3:0] is ignored. TXDC3 is the Most Significant Bit.

150

TXERC

I, TTL Transmit Error MII C. Synchronousto the TXCLK's rising edge.

When TXERC is asserted for one or more TXCLK period while

TXENC is also asserted, one or more "HALT" symbols will present

at TDAT4_0

151

RXDVC

O, TTL Receive Data Valid MII C. Synchronous to RXCLK's rising edge.

This signal remains asserted through the whole frame, starting with

the start-of-frame delimiter and excluding any end-of-frame

deliminter. High impedance after reset.

152

EDATACT

O, TTL Expansion DATa Activity. When XRC is outputing data onto expan-

sion EDAT, this pin will be asserted high. User can use this pin to

control external EDAT bus switch in case multiple HUBs applica-

tion is necessary.

P/N:PM0342

REV. 1.4, NOV. 07, 1996

7

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