MX98741 Ver la hoja de datos (PDF) - Macronix International
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componentes Descripción
Lista de partido
MX98741 Datasheet PDF : 34 Pages
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MX98741
PAD #
30-37
205
116
117-120
121
122
123
153
Name
XACTLED[0:7]
XCOLED
TXENA
TXDA[0:3]
TXERA
RXDVA
CRSA
MDIO
E. LED Pins, 9 pins
I/O
Description
O, TTL Activity LED. Active Low. This pin provides a minimum 80ms ON
time (low) and 20ms OFF time (high) for activities on each port.
External buffers are necessary to drive LEDs.
O, MII Collision LED. This pin is capable of driving LED directly to display
Activity status. The ON (active low) time and OFF (active high)
time of LED's is 80ms and 20ms respectively.
F. Media Independent Interface (MII), 33 pins
I, TTL Transmit Enable MII A. Synchronous to the TXCLK's rising edge. It
is asserted by the MAC with the first nibble of the preamble and
remains asserted while all nibbles to be transmitted are presented.
I, TTL Transmit Data MII A. Synchronous to the TXCLK's rising edge. For
each TXCLK period in which TXENA is asserted, TXDA[3:0] are
also driven by the MAC. While TXENA is de-asserted, the value of
TXDA[3:0] is ignored. TXDA3 is the Most Significant Bit.
I, TTL Transmit Error MII A. Synchronous to the TXCLK's rising edge.
When TXERA is asserted for one or more TXCLK period while
TXENA is also asserted, one or more "HALT" symbols will present
at TDAT4_0.
O, TTL Receive Data Valid MII A. Synchronous to RXCLK's rising edge.
This signal remains asserted through the whole frame, starting with
the start-of-frame delimiter and excluding any end-of-frame delim-
iter. High impedance after reset.
O, TTL Carrier Sense MII A. In TX mode, synchronous to RXCLK. This
pin is asserted when (1) the receiving medium is not idle, or (2) the
transmitting medium is not idle in the half-duplex mode. High im-
pedance after reset.
I/O, TTL Management Data Input/Output. A bi-directional signal. After re-
set, this pin is in high-impedance state. The selection of input/
output direction is based on IEEE 802.3u management functions
(Section 22.2.4). Low after reset due to internally pull-down. When
RDXWR is low (i.e. Write operation, MDIO will be forced to low to
disable the function of MDC and MDIO. i.e. Programming internal
registers through register access pins owns higher priority.
P/N:PM0342
REV. 1.4, NOV. 07, 1996
6
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