MPC92432 Ver la hoja de datos (PDF) - Motorola => Freescale
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MPC92432 Datasheet PDF : 20 Pages
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MPC92432
Freescale Semiconductor, Inc.
This two-step procedure can be performed by a single I2C
transaction or by multiple, independent I2C transactions. An
alternative way to achieve small PLL frequency changes is to
use the increment or decrement commands of the synthesizer,
which have an immediate effect on the PLL frequency.
Synthesizer – PLL
PN
M
LOAD/GET
Configuration Latches
PLL_L (R/W) PLL_H (R/W) CMD (W)
0x00
0x01
0xF0
I2C Registers
I2C Access
Figure 3. I2C Mode Register Set
Figure 3 illustrates the synthesizer register set. PLL_L and
PLL_H store a PLL configuration and are fully accessible
(Read/Write) by the I2C bus. CMD (Write only) accepts
commands (LOAD, GET, INC, DEC) to update registers and for
direct PLL frequency changes.
Set the synthesizer frequency:
1) Write the PLL_L and PLL_H registers with a new con-
figuration (see Table 14 and Table 15 for register
maps)
2) Write the LOAD command to update the PLL dividers
by the current PLL_L, PLL_H content.
Read the synthesizer frequency:
1) Write the GET commands to update the PLL_L, PLL_H
registers by the PLL divider setting
2) Read the PLL_L, PLL_H registers through I2C
Change the synthesizer frequency in small steps:
1) Write the INC or DEC command to change the PLL fre-
quency immediately. Repeat at any time if desired.
LOAD and GET are inverse command to each other. LOAD
updates the PLL dividers and GET updates the configuration
registers. A fast and convenient way to change the PLL
frequency is to use the INC (increment M) and DEC (decrement
M) commands of the synthesizer. INC (DEC) directly
increments (decrements) the PLL-feedback divider M and
immediately changes the PLL frequency by the smallest step G
(see Table 7 for the frequency granularity G). The INC and DEC
commands are designed for multiple and rapid PLL frequency
changes as required in frequency margining applications. INC
and DEC do not require the user to update the PLL dividers by
the LOAD command, INC and DEC do not update the PLL_L
and PLL_H registers either (use LOAD for an initial PLL divider
setting and, if desired, use GET to read the PLL configuration).
Note that the synthesizer does not check any boundary
conditions such as the VCO frequency range. Applying the INC
and DEC commands could result in invalid VCO frequencies
(VCO frequency beyond lock range).
Register Maps
Table 13. Configuration Registers
Address
0x00
0x01
0xF0
Name
PLL_L
PLL_H
CMD
Content
Least significant 8 bits of M
Most significant 2 bits of M, P, NA,
NB, and lock state
Command register (write only)
Access
R/W
R/W
W only
Register 0x00 (PLL_L) contains the least significant bits of
the PLL feedback divider M.
Table 14. PLL_L (0x00, R/W) Register
Bit
7
6
5
4
3
2
1
0
Name M7 M6 M5 M4 M3 M2 M1 M0
Register content:
M[7:0]
PLL feedback-divider M, bits 7–0
Register 0x01 (PLL_H) contains the two most significant bits
of the PLL feedback divider M, four bits to control the PLL post-
dividers N and the PLL pre-divider P. The bit 0 in PLL_H register
indicates the lock condition of the PLL and is set by the
synthesizer automatically. The LOCK state is a copy of the PLL
lock signal output (LOCK). A write-access to LOCK has no
effect.
Table 15. PLL_H (0x01, R/W) Register
Bit
7
6
5
4
3
2
Name M9 M8 NA2 NA1 NA0 NB
1
0
P LOCK
Register content:
M[9:8] PLL feedback-divider M, bits 9–8
NA[2:0]
NB
P
PLL post-divider NA, see Table 9
PLL post-divider NB, see Table 10
PLL pre-divider P, see Table 8
LOCK Copy of LOCK output signal (read-only)
Note that the LOAD command is required to update the PLL
dividers by the content of both PLL_L and PLL_H registers.
Register 0xF0 (CMD) is a write-only command register.
The purpose of CMD is to provide a fast way to increase or
decrease the PLL frequency and to update the registers. The
register accepts four commands, INC (increment M), DEC
(decrement M), LOAD and GET (update registers). It is
MOTOROLA
10
TIMING SOLUTIONS
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