MPC92432 Ver la hoja de datos (PDF) - Motorola => Freescale
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MPC92432 Datasheet PDF : 20 Pages
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Freescale Semiconductor, Inc.
MPC92432
Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TJ = –40°C to +85°C)1 2
Symbol
Characteristics
Min
Typ
Max
Unit Condition
fXTAL Crystal Interface Frequency Range
15
16
20
MHz
fREF FREF_EXT Reference Frequency Range
15
—
20
MHz
fVCO VCO Frequency Range3
1360
—
2720
MHz
fMAX Output Frequency4
N= ÷2
680
—
1360
MHz
N= ÷4
340
—
680
MHz
N= ÷8
170
—
340
MHz
N= ÷16
85
—
170
MHz
N= ÷32
42.5
—
85
MHz
N= ÷64
21.25
—
42.5
MHz
fSCL Serial Interface (I2C) Clock Frequency
0
—
0.4
MHz
tP,MIN Minimum Pulse Width
(P_LOAD)
50
—
ns
DC Output Duty Cycle
45
50
55
%
tSK(O) Output-to-Output Skew
Same frequency
—
—
25
ps
Different frequency
—
50
ps
tr, tf Output Rise/Fall Time (QA, QB)
0.05
—
0.3
ns 20% to 80%
tr, tf Output Rise/Fall Time (SDA)
—
—
250
ns CL = 400 pF
tP_EN Output Enable Time (CLKSTOPx to QA, QB)
TFOUT
—
2 · TFOUT
T = period of Qx
tP_DIS Output Enable Time (CLKSTOPx to QA, QB)
0.5 · TFOUT
—
1.5 · TFOUT
T = period of Qx
tJIT(CC) Cycle-to-Cycle Jitter
N= ÷2
—
N= ÷4
—
N= ÷8
—
N= ÷16
—
N= ÷32
—
N= ÷64
—
—
TBD
ps
—
TBD
ps
—
25
ps
—
25
ps
—
TBD
ps
—
TBD
ps
tJIT(CC) Period Jitter (RMS)
fOUT = 250 MHz
—
Any other frequency
—
—
10
ps
—
TBD
ps
tLOCK Maximum PLL Lock Time
—
—
10
ms
1. AC specifications are subject to change
2. AC characteristics apply for parallel output termination of 50 Ω to VTT
3. The input frequency fXTAL, the PLL divider M and P must match the VCO frequency range: fVCO = fXTAL · M ÷ P. The feedback divider M is
limited to 170 <= M <= 340 (for P = 2) and 340 <= M <= 680 (for P = 4) for stable PLL operation
4. Output frequency for QA, QB if NB=0. With NB=1 the QB output frequency is half of the QA output frequency
TIMING SOLUTIONS
7
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