MPC92432
Freescale Semiconductor, Inc.
REF_CLK
XTAL1
XTAL2
REF_SEL
TEST_EN
SDA
SCL
ADR[1:0]
PLOAD
M[9:0]
NA[2:0]
NB
P
CLK_STOPx
BYPASS
MR
XTAL
÷P
fREF
PLL
Configuration
Registers
I2C Control
fVCO
÷NA
PLL
÷M
Figure 1. MPC92432 — Generic Logic Diagram
fQA
fQB
÷NB
QA
QB
LOCK
36 35 34 33 32 31 30 29 28 27 26 25
GND
37
24
M9
NA2
38
23
M8
NA1
39
22
M7
NA0
40
21
M6
PLOAD
41
20
M5
VCC
42
MR
43
MPC92432
19
GND
18
M4
SDA
44
17
M3
SCL
45
16
M2
ADR1
46
15
M1
ADR0
47
14
M0
P
48
13
1 2 3 4 5 6 7 8 9 10 11 12
VCC
It is recommended to use an external
RC filter for the analog VCC_PLL supply
pin. Please see the application section
for details.
Figure 2. 48-Lead Package Pinout (Top View)
MOTOROLA
2
TIMING SOLUTIONS
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