MPC92432 Ver la hoja de datos (PDF) - Motorola => Freescale
Número de pieza
componentes Descripción
Lista de partido
MPC92432 Datasheet PDF : 20 Pages
| |||
MPC92432
Freescale Semiconductor, Inc.
APPLICATION INFORMATION
Output Frequency Configuration
The MPC92432 is a programmable frequency source
(synthesizer) and supports an output frequency range of
21.25 – 1360 MHz. The output frequency fOUT is a function of
the reference frequency fREF and the three internal PLL dividers
P, M, and N. fOUT can be represented by this formula:
fOUT = (fREF ÷ P) · M ÷ (NA, B)
(1)
The M, N and P dividers require a configuration by the user
to achieve the desired output frequency. The output divider,
NA, determines the achievable output frequency range (see
Table 7). The PLL feedback-divider M is the frequency
multiplication factor and the main variable for frequency
synthesis. For a given reference frequency fREF, the PLL
feedback-divider M must be configured to match the specified
VCO frequency range in order to achieve a valid PLL
configuration:
Table 7. Frequency Ranges (fREF = 16 MHz)
fOUT (QA) [MHz]
NA
M
P
680 – 1360
170 – 340
2
NA=2
340 – 680
4
340 – 680
170 – 340
2
NA=4
340 – 680
4
170 – 340
170 – 340
2
NA=8
340 – 680
4
85 – 170
170 – 340
2
NA=16
340 – 680
4
42.5 – 85
170 – 340
2
NA=32
340 – 680
4
170 – 340
2
21.25 – 42.5
NA=64
340 – 680
4
G [MHz]
4
2
2
1
1
0.5
0.5
0.25
0.25
0.125
0.125
0.0625
fVCO = (fREF ÷ P) · M and
(2)
1360 ≤ fVCO ≤ 2720
(3)
The output frequency may be changed at any time by
changing the value of the PLL feedback divider M. The smallest
possible output frequency change is the synthesizer granularity
G (difference in fOUT when incrementing or decrementing M). At
a given reference frequency, G is a function of the PLL pre-
divider P and post-divider N:
G = fREF ÷ (P · NA,B)
(4)
The NB divider configuration determines if the output QB
generates a 1:1 or 2:1 frequency copy of the QA output signal.
The purpose of the PLL pre-divider P is to situated the PLL into
the specified VCO frequency range fVCO (in combination with
M). For a given output frequency, P = 4 results in a smaller
output frequency granularity G, P = 2 results a larger output
frequency granularity G and also increases the PLL bandwidth
compared to the P = 2 setting.
The following example illustrates the output frequency range
of the MPC92432 using a 16-MHz reference frequency.
Example Output Frequency Configuration
If a reference frequency of 16 MHz is available, an output
frequency at QA of 250 MHz and a small frequency granularity
is desired, the following steps would be taken to identify the
appropriate P, M, and N configuration:
1. Use Table 7 to select the output divider, NA, that matches
the desired output frequency or frequency range.
According to Table 7, a target output frequency of
250 MHz falls in the fOUT range of 170 to 340 MHz and
requires to set NA = 8
2. Calculate the VCO frequency fVCO = fOUT · NA, which is
2000 MHz in this example.
3. Determine the PLL feedback divider: M = fVCO ÷ P.
The smallest possible output granularity in this example
calculation is 500 kHz (set P = 4). M calculates to a value
of 2000 ÷ 4 = 500.
4. Configure the MPC92432 with the obtained settings:
M[9:0] = 0111110100b (binary number for M=500)
NA[2:0] = 010
P=1
(÷8 divider, see Table 9)
(÷4 divider, see Table 8)
NB = 0
(fOUT, QB = fOUT, QA)
5. Use either parallel or serial interface to apply the setting.
The I2C configuration byte for this examples are:
PLL_H=01010010b and PLL_L=11110100b.
See Table 14 and Table 15 for register maps.
MOTOROLA
8
For More Information On This Product,
Go to: www.freescale.com
TIMING SOLUTIONS
Share Link: 