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78Q2120

10/100BASE-TX Ethernet Transceiver

TDK Corporation 

78Q2120

10/100BASE-TX

Ethernet Transceiver

REGISTER DESCRIPTION

The 78Q2120 implements ten 16-bit registers which are accessible via the MDIO and MDC pins. The supported

registers are shown below. Unsupported registers will be read as all zeros. All of the registers respond to the

broadcast address, PHYAD value 00000.

The MII management 16-bit register set implemented in the 78Q2120 is as follows:

ADDRESS

SYMBOL NAME

0

MR0

Control

1

MR1

Status

2

MR2

PHY Identifier 1

3

MR3

PHY Identifier 2

4

MR4

Auto-Negotiation Advertisement

5

MR5

Auto-Negotiation Link Partner Ability

6

MR6

Auto-Negotiation Expansion

7

MR7

(Not implemented, read as zero)

8-15

MR8-15 (Reserved, read as zero)

16

MR16 Vendor Specific

17

MR17 Interrupt Control/Status Register

18

MR18 Diagnostic Register

Note: MR 3.3:0 contains revision specific data.

RESET VALUE (HEX)

(3100)

(7809)

0300

(E542)

(01E1)

0000

0000

0000

0000

0540

0000

(0000)

LEGEND

TYPE

R

RC

0/1

DESCRIPTION

Readable by management

Cleared on a read operation

Default value upon power-up or reset

TYPE

W

SC

(0/1)

DESCRIPTION

Write-able by management

Self clearing, write-able

Default value dependent on pin setting. The value

in brackets indicates typical case.

10

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