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78Q2120

10/100BASE-TX Ethernet Transceiver

TDK Corporation 

MDIO pin at the rising edge of the MDC clock signal.

Once the preamble is received, the station

management control logic looks for the start-of-

frame sequence and a read or write op-code,

followed by the PHYAD and REGAD fields. For a

read operation, the MDIO port becomes enabled as

an output and the register data is loaded into a shift

register for transmission. The 78Q2120 can work

with a one bit preamble rather than the 32 bits

proscribed by IEEE-802.3. This allows for faster

programming of the registers. If a register does not

exist at an address indicated by the REGAD field or

if the PHYAD field does not match the 78Q2120

PHYAD indicated by the PHYAD pins, a read of the

MDIO port will return all ones. For a write operation,

the data is shifted in and loaded into the appropriate

register after the sixteenth data bit has been

received. Writes to registers not supported by the

78Q2120 are ignored.

When the PHYAD field is all zeros, the Station

Management Entity (STA) is requesting a broadcast

data transaction. All PHYs sharing the same

Management Interface must respond to this

broadcast request. All 78Q2120 will respond to the

broadcast data transaction.

ADDITIONAL FEATURES

LED INDICATORS

There are seven LED pins that can be used to

indicate various states of operation of the 78Q2120.

There is an LED pin that indicates the link is up

(LEDL), others that indicate the 78Q2120 is either

transmitting (LEDTX) or receiving (LEDRX), one that

signals a collision event (LEDCOL), two more that

reflect the data rate (LEDBTX and LEDBT), and one

that reflects full duplex mode of operation

(LEDFDX).

78Q2120

10/100BASE-TX

Ethernet Transceiver

GENERAL PURPOSE I/O INTERFACE

(80-TQFP ONLY)

The 78Q2120 80-pin TQFP has a two pin, bi-

directional, general purpose interface that can be

used for external control or to monitor external

signals. The direction of these pins and data that is

either driven or read from these pins is configured

via bits MR16.9:6 as detailed in the Vendor Specific

Register description of MR16.

INTERRUPT PIN

The 78Q2120 has an Interrupt pin (INTR) that is

asserted whenever any of the eight interrupt bits of

MR17.7:0 are set. These interrupt bits can be disabled

via MR17.15:8 Interrupt Enable bits. The active level

of the INTR pin is controlled by the Interrupt Level bit,

MR16.14. When the INTR pin is not asserted, the pin

is held in a high impedance state.

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