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78Q2120

10/100BASE-TX Ethernet Transceiver

TDK Corporation 

78Q2120

10/100BASE-TX

Ethernet Transceiver

SQE TEST

The 78Q2120 supports the signal quality error

(SQE) function detailed in IEEE-802.3. At an

interval of 1µs after each negative transition of the

TXEN pin in 10BASE-T mode, the COL pin will go

high for a period of 1µs. This function can be

disabled through register bit MR16.11.

NATURAL LOOPBACK

When the 78Q2120 is transmitting and not receiving

on the twisted pair media, data on the TXD pins is

looped back onto the RXD pins. During a collision,

data from the RXI pins is routed to the RXD pins.

The natural loopback function can be enabled

through register bit MR16.10.

REPEATER MODE

When the RPTR pin is high or register bit MR 16.15

is set the 78Q2120 is placed in repeater mode. In

this mode, full duplex operation is prohibited, CRS

responds only to receive activity and, in 10BASE-T

mode, the SQE test function is disabled.

AUTO-NEGOTIATION

The 78Q2120 supports the auto-negotiation

functions of Clause 28 of IEEE-802.3. This function

can be enabled via a pin strap to the device or

through registers. If the ANEGA pin is tied high, the

auto-negotiation function defaults to on and bit

MR0.12, ANEGEN, is high after reset. Software can

disable the auto-negotiation function by writing to bit

MR0.12 If the ANEGA pin is tied low the function

defaults to off and bit MR0.12 is set low after reset

and cannot be written to.

The contents of register MR4 are sent to the

78Q2120’s link partner during auto-negotiation,

coded in fast link pulses. Bits MR4.8:5 reflect the

state of the TECH[2:0] pins after reset. If TECH[2:0]

= 111, then all 4 bits are high. If TECH[2:0] = 001,

then only bit 5 is high. After reset, software can

change any of these bits from a 1 to a 0; but not

from a 0 to a 1. Therefore, a technology permitted by

the setting of the TECH pins can be disabled, but

one not permitted cannot be enabled.

With auto-negotiation enabled, the 78Q2120 will

start sending fast link pulses at power on, loss of link

or a command to restart. At the same time it will

look for either 10BASE-T idle, 100BASE-TX idle or

fast link pulses from its link partner. If either idle

pattern is detected, the 78Q2120 configures itself in

half-duplex mode at the appropriate speed. If it

detects fast link pulses, it decodes and analyzes the

link code transmitted by the link partner. When

4

three identical link code words are received (ignoring

the acknowledge bit) the link code word is stored in

register 5. Upon receiving three more identical link

code words, with the acknowledge bit set, the

78Q2120 configures itself to the highest priority

technology common to the two link partners. The

technology priorities are, in descending order:

100BASE-TX, Full Duplex

100BASE-TX, Half Duplex

10BASE-T, Full Duplex

10BASE-T, Half Duplex

Once auto-negotiation is complete, register bits

MR18.11:10 will reflect the actual speed and duplex

that was chosen.

If auto-negotiation fails to establish a link for any

reason, register bit MR18.12 will reflect this and auto

negotiation will restart from the beginning. Writing a

one to bit MR0.9, RANEG, will also cause auto-

negotiation to restart.

MEDIA INDEPENDENT INTERFACE

MII Transmit and Receive Operation

The MII interface on the 78Q2120 provides

independent transmit and receive paths for both

10Mb/s and 100Mb/s data rates as described in

Clause 22 of the IEEE-802.3 standard.

The transmit clock, TX_CLK, provides the timing

reference for the transfer of TX_EN, TXD[3:0], and

TX_ER signals from the MAC to the 78Q2120.

TXD[3:0] is captured on the rising edge of TX_CLK

when TX_EN is asserted. TX_ER is also captured

on the rising edge of TX_CLK and is asserted by the

MAC to request that an error code group be

transmitted. The assertion of TX_ER has no affect

when the 78Q2120 is operating in 10BASE-T mode.

The receive clock, RX_CLK, provides the timing

reference to transfer RX_DV, RXD[3:0], and RX_ER

signals from the 78Q2120 to the MAC. RX_DV

transitions synchronously with respect to RX_CLK and

is asserted when the 78Q2120 is presenting valid data

on RXD[3:0]. RX_ER is asserted when a code group

violation has been detected in the current receive

packet and is also synchronous to RX_CLK.

STATION MANAGEMENT INTERFACE

The station management interface consists of

circuitry which implements the serial protocol as

described in Clause 22.2.4.4 of IEEE-802.3. A 16-bit

shift register receives serial data applied to the

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