78Q2120 Ver la hoja de datos (PDF) - TDK Corporation
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78Q2120 Datasheet PDF : 33 Pages
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78Q2120
10/100BASE-TX
Ethernet Transceiver
PIN DESCRIPTION
LEGEND
TYPE
A
O
S
DESCRIPTION
Analog Pin
Digital Output
Supply
TYPE DESCRIPTION
I Digital Input
I/O Digital Bi-directional Pin
OZ Tri-stateable digital output
MII (MEDIA INDEPENDENT INTERFACE)
PIN
TX_CLK
TX_EN
TXD[3:0]
TX_ER
CRS
COL
RX_CLK
RX_DV
RXD[3:0]
RX_ER
64-PIN
27
28
32-29
26
34
33
24
23
19-22
25
80-PIN
33
34
40-37
32
42
41
30
29
23-26
31
TYPE
OZ
I
I
I
OZ
OZ
OZ
OZ
OZ
OZ
DESCRIPTION
TRANSMIT CLOCK: TX_CLK is a continuous clock which provides a
timing reference for the TX_EN, TX_ER and TXD[3:0] signals from the
MAC. The clock frequency is 25MHz in 100BASE-TX mode and
2.5MHz in 10BASE-T mode. This pin is tri-stated in isolate mode.
TRANSMIT ENABLE: TX_EN is asserted by the MAC to indicate that
valid data for transmission is present on the TXD[3:0] pins.
TRANSMIT DATA: TXD[3:0] receives data from the MAC for
transmission on a nibble basis. This data is captured on the rising
edge of TX_CLK when TX_EN is high.
TRANSMIT ERROR: TX_ER is asserted high to request that an error
code-group be transmitted when TX_EN is high. In PCS bypass mode
this pin becomes the higher-order bit of the transmit 5-bit code group.
CARRIER SENSE: When the 78Q2120 is not in repeater mode, CRS
is high whenever a non-idle condition exists on either the transmitter
or the receiver. In repeater mode, CRS is only active when a non-idle
condition exists on the receiver. This pin is tri-stated in isolate mode.
COLLISION: COL is asserted high when a collision has been
detected on the media. In 10BASE-T mode COL is also used for the
SQE test function. This pin is tri-stated in isolate mode.
RECEIVE CLOCK: RX_CLK is a continuous clock which provides a
timing reference to the MAC for the RX_DV, RX_ER and RXD[3:0]
signals. The clock frequency is 25MHz in 100BASE-TX mode and
2.5MHz in 10BASE-T mode. To reduce power consumption, in
100BASE-TX mode, the 78Q2120 provides an optional mode enabled
through MR16.0 in which RX_CLK is held inactive (low) when no
receive data is detected. This pin is tri-stated in isolate mode.
RECEIVE DATA VALID: RX_DV is asserted high to indicate that valid
data is present on the RXD[3:0] pins. In 100BASE-TX mode, it
transitions high with the first nibble of preamble and is pulled low
when the last data nibble has been received. In 10BASE-T mode it
transitions high when the start-of-frame delimiter (SFD) is detected.
This pin is tri-stated in isolate mode.
RECEIVE DATA: Received data is provided to the MAC via RXD[3:0].
These pins are tri-stated in isolate mode.
RECEIVE ERROR: RX_ER is asserted high when an error is detected
during frame reception. In PCS bypass mode this pin becomes the
higher-order bit of the receive 5-bit code group. This pin is tri-stated in
isolate mode.
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