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MTD800

Integrated Fast Ethernet Controller

Myson Century Inc 

MYSON

TECHNOLOGY

MTD 800

(Preliminary)

Name

Data Par ity Er ror

Detected

Field

Bit 8

DEVSEL_ Timing Bit

9~10

Reser ved

Received Tar get

Abor t

Bit 11

Bit 12

Received master

Abor t

Bit 13

Reser ved

Detected Par ity

Er r or

Bit 14

Bit 15

Descr iption

The value is 0 after har dware r eset.

This field is read only and write-one to clear. This bit is set when

three conditions are true concurrently.

(1) The device asserts PERR_ itself or it detects asserted PERR_.

(2) The device is as a bus master during a operation in which a error

occurred.

(3) The Parity Error Response bit is set.

This field is har dwir ed to 01H.

A value of 01H indicates the device asserts DEVSEL_ with medium

speed.

This field is har dwir ed to 0.

The value is 0 after har dware r eset.

This field is read only and write-one to clear. This bit is set when-

ever the device’s master detects a termination with Target Abort.

The value is 0 after har dware r eset.

This field is read only and write-one to clear. This bit is set when-

ever the devices’s master terminates the transaction with Master

Abort.

This field is har dwir ed to 0.

The value is 0 after har dware r eset.

This field is read only and write-one to clear. This bit is set when-

ever the device detects a parity error.

4.1.4 Burst Register ( CFBR)

Table 4.5 The contents of Burst Registers

4.1.5 Base Address Register

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MTD800 Revision 0.0 07/20/1999

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