MTD800 Ver la hoja de datos (PDF) - Myson Century Inc

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MTD800

Integrated Fast Ethernet Controller

Myson Century Inc 

MYSON

TECHNOLOGY

MTD 800

(Preliminary)

Name

Location Width Descr iption

Cache Line 0CH

Size

8-Bit

The value is 00H after har dware r eset.

This field is readable and writable. This register specifies the

cache line size for one burst. All of Memory Write and Inval-

idate, Memory Read Line and Memory Read Multiple cache-

oriented commands must transfer data in a burst limited by

Cache Line Size. The chip only supports CLS of 8, 16 and 32

longwords. If an attempt is made to write an unsupported

value to this register, the chip behaves as if a value of zero

was written.

Latency

Timer

0DH

8-Bit The value is 00H after har dware r eset.

This field is readable and writable. This register limits the

maximum time in which the device is permitted to access the

bus.

Min_Gnt

3EH

8-Bit The value is 0 after har dware reset.

At final state, this field is loaded from EEPROM. This regis-

ter indicates how long the device needs to convey the data in

a burst . It is in a unit of 0.25us

Max_Lat

3FH

8-Bit The value is 0 after har dware reset.

At final state, this field is loaded from EEPROM. This regis-

ter indicates how often the device needs to convey the data.

It is in a unit of 0.25us.

There are three base address registers. They are located at configuration address of 10H, 14H and 30H

respectively. Following are the descriptions of these registers.

Table 4.6 I/O Map Base Address Register ( CFIOBR )

Name

Field

IO Space Indicator Bit 0

Descr iption

This Field is har dwir ed to 1.

Reser ved

IO Space Size

Bit 1

Bit 2~6

A value of 1 indicates that the register presents IO Base Address

This field is har dwir ed to 0.

This field is har dwir ed to 0.

IO Base Address

Bit

7~31

These bits are hardwired to 0 to indicate the device requires IO

space in size of 128 longwords.

The value is 0 after har dware r eset.

These bits is readable and writable. This field can be programmed

by BIOS to specify the base address.

Table 4.7 Memory Map Base Address Register ( CFMBR )

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MTD800 Revision 0.0 07/20/1999

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