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RTL8139D Ver la hoja de datos (PDF) - Unspecified

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RTL8139D Datasheet PDF : 67 Pages
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RTL8139DL
Datasheet
4.6. Attachment Unit Interface
Symbol
TXD+
TXD-
RXIN+
RXIN-
X1
X2
Type
O
O
I
I
I
O
Pin No
72
71
68
67
61
60
Description
100/10BASE-T transmit (Tx) data.
100/10BASE-T receive (Rx) data.
25 MHz crystal/OSC. input.
Crystal feedback output: This output is used in crystal connection only.
It must be left open when X1 is driven with an external 25 MHz oscillator.
4.7. Multi-Function Interface
Symbol
REQB2
GNTB2
IDSEL2
Type
IN
T/S,O
O
Pin No
53
54
78
Description
Request2: The 2nd device will assert this pin low to request the
ownership of the PCI bus.
Grant2: This signal is asserted low to indicate that the central arbiter
has granted ownership of the bus to the 2nd device.
Initialization Device Select 2: Used as a chip-select during
configuration read and write transactions to the 2nd device.
4.8. Test And Other Pins
Symbol
RTT3
RTSET
Type
TEST
I/O
Pin No
63
65
VCTRL
Analog
55
ROMCS/OEB
O
35
CLKRUNB
I/O
52
NC
-
7,40,69,76
Description
Chip test pin.
This pin must be pulled low by a resistor. Please refer to the application
circuit for correct value.
Use this pin and an external PNP type transistor to generate +2.5V for
the RTL8139D(L).
ROM Chip Select and Output Enable: This is the chip select signal
and output enable for the Boot PROM.
Clock Run: This signal is used by the RTL8139D(L) to request starting
(or speeding up) the clock, CLK. CLKRUNB also indicates the clock
status. For the RTL8139D(L), CLKRUNB is an open drain output as
well as an input. The RTL8139D(L) requests the central resource to
start, speed up, or maintain the interface clock by the assertion of
CLKRUNB. For the host system, it is an S/T/S signal. The host system
(central resource) is responsible for maintaining CLKRUNB asserted,
and for driving it high to the negated (deasserted) state.
Reserved
Single Chip Multifunction 10/100 Ethernet Controller w/Power Management 7 Track ID: JATR-1076-21 Rev. 1.2

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